Multi-Processor State Data Synchronization via Periodic Update Cycles

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Solution Overview

Problem

Multi-processor systems face challenges in coordinating state data synchronization, leading to potential data loss and customer dissatisfaction due to inappropriate timing of communications between processors.

Innovation Solution

A system that synchronizes state data by executing a first processor based on initial state data, detecting changes using sensors, and transitioning to next state data at a predefined progress position within an update cycle, ensuring all processors execute based on current state data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If processors communicate state data continuously, then data freshness is improved, but system complexity and communication overhead increase

Engineering Contradiction:
Improvedata freshnessVSAvoidcommunication coordination
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements periodic update cycles where state data is synchronized at predetermined intervals rather than continuously. Each update cycle has a specific progress position where synchronization occurs, reducing communication overhead while maintaining data freshness. The processor executes based on initial state data throughout the cycle, then transitions to next state data at the synchronization point.

Inventive Principle:
Principle #19Periodic action

2Speed

If state data is updated frequently, then system responsiveness is improved, but data loss risk increases due to timing issues

Engineering Contradiction:
Improvesystem responsivenessVSAvoiddata loss
Core Design Contradiction:
SpeedVSLoss of information

Solution Approach 1:

The patent designates next state data before the update cycle completes, preparing the transition in advance. At the predetermined progress position, the system locks the modified state data as next state data before the processor transitions execution. This preliminary designation prevents data loss by ensuring the target state is ready before the switch occurs.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary mechanism where modified state data is held in a designated next state data buffer before becoming the active initial state data. This intermediary storage prevents data loss by decoupling the state modification from the processor execution transition, allowing safe data handoff between update cycles.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If processors execute immediately on state changes, then real-time performance is improved, but synchronization accuracy deteriorates

Engineering Contradiction:
Improveexecution speedVSAvoidsynchronization accuracy
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The patent implements dynamic execution where the processor operates in two modes: executing based on initial state data during the update cycle, then transitioning to execute based on next state data after synchronization. This dynamic switching allows real-time performance during execution while achieving high synchronization accuracy at the transition points.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20240232126A1Multi-processor synchronization
Publication Date: 2024.07.11 MICROSOFT TECHNOLOGY LICENSING LLC
  • US20240232126A1 patent drawing
  • US20240232126A1 patent drawing
  • US20240232126A1 patent drawing

AI summary

A method of synchronizing system state data is provided. The method includes executing a first processor based on initial state data during an update cycle, wherein the initial state data represents a state of the system prior to initiation of the update cycle, detecting changes in state of the system by the first processor using sensors, the changes in state being added to a record of modified state data until a predefined progress position within the update cycle, designating the modified state data as next state data, based on reaching the predefined progress position within the update cycle, and transitioning from execution of the first processor based on the initial state data to execution of the first processor based on the next state data, based on completion of the update cycle.