Processor Storage Instruction Merging for Memory Bandwidth
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Solution Overview
Problem
The high strain on memory subsystems due to multiple load and store operations in modern programming languages, which limits potential performance increases because of bottlenecks in load and store paths.
Innovation Solution
A processor unit with a detection logic unit that identifies and combines spatially close storage instructions into a single combined instruction, reducing the number of dispatch and issue slots, and allowing cache accesses to be performed in parallel, thereby reducing bandwidth to the memory subsystem.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple load and store operations are generated by compilers for objects and classes, then programming flexibility and portability are improved, but memory subsystem strain increases and performance is limited due to bottlenecks in load and store paths
Solution Approach 1:
The patent combines multiple adjacent storage instructions (load or store operations) into a single merged storage instruction. The detection logic identifies when multiple instructions operate on adjacent memory locations, and the combination unit merges them into one instruction that specifies multiple memory locations and their corresponding data values, thereby reducing the number of separate memory operations and alleviating memory subsystem strain
2Ease of operation
If multiple separate storage instructions are executed, then precise control over individual memory operations is maintained, but the number of dispatch and issue slots increases and processing efficiency decreases
Solution Approach 1:
The patent merges multiple storage instructions into a single combined instruction that maintains precise control over each individual memory operation. The combined instruction specifies multiple pairs of memory locations and data values, allowing the processor to control each storage operation precisely while executing them as a single unified instruction, thereby reducing dispatch overhead and improving processing efficiency
3Productivity
If instruction combination is implemented to reduce memory operations, then bandwidth to memory subsystem is reduced and performance increases, but instruction complexity and detection requirements increase
Solution Approach 1:
The patent segments the instruction processing into distinct functional units: a detection logic unit that identifies candidate instructions for merging, a combination unit that performs the merging operation, and an execution unit that processes the combined instruction. This segmentation allows the complex merging logic to be modular and manageable, reducing the overall system complexity while achieving improved memory bandwidth utilization
Data Source
AI summary
A processor unit for processing storage instructions. The processor unit comprises a detection logic unit configured to identify at least two storage instructions for moving addressable words between registers of the processor unit and neighboring storage locations. The processor unit further comprises a combination unit configured to combine the identified instructions into a single combined instruction; and a data movement unit configured to move the words using the combined instruction.