Processor Storage Sharing via Busy Signal Control
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Solution Overview
Problem
In complex system chips, the use of multiple independent flash memories for each processor increases hardware costs and power consumption, necessitating a method for multiple processors to share a single external storage device without introducing side effects.
Innovation Solution
A method where multiple processors alternate between access and detection modes, controlling a busy signal to indicate permission to access the storage device, allowing them to share the storage device efficiently without increasing costs or introducing malfunctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each processor uses one independent flash memory, then reliability is improved, but hardware cost and power consumption increase
Solution Approach 1:
Multiple processors share a single flash memory device through a bus interface, merging what would otherwise be separate storage resources. This reduces the total quantity of flash memory devices needed while maintaining system functionality through coordinated access control.
Solution Approach 2:
The shared flash memory device serves multiple processors universally, acting as a common resource for the entire system rather than being dedicated to a single processor. This multi-functional usage reduces hardware quantity while maintaining reliability through proper access management.
2Reliability
If each processor uses one independent flash memory, then reliability is improved, but power consumption increases
Solution Approach 1:
Multiple processors share a single flash memory device through a bus interface, merging what would otherwise be separate storage resources. This reduces the total quantity of flash memory devices needed while maintaining system functionality through coordinated access control.
3Quantity of substance
If multiple processors share one storage device, then hardware cost is reduced, but system complexity increases
Solution Approach 1:
A busy signal acts as an intermediary control mechanism between multiple processors and the shared flash memory. This simple binary signal coordinates access without requiring complex arbitration logic, managing the shared resource while minimizing added system complexity.
4Quantity of substance
If multiple processors share one storage device, then hardware cost is reduced, but control complexity increases
Solution Approach 1:
A busy signal acts as an intermediary control mechanism between multiple processors and the shared flash memory. This simple binary signal coordinates access without requiring complex arbitration logic, managing the shared resource while minimizing added system complexity.
Solution Approach 2:
Each processor monitors the busy signal and autonomously determines when to access the flash memory based on the signal state. This self-service approach allows processors to independently manage their own access timing without requiring centralized control, simplifying the control mechanism.
Data Source
AI summary
A method for sharing a storage device among multiple processors and an associated electronic device are provided. The method includes: controlling a first processor and a second processor to operate in an access mode and a detection mode, respectively; in response to the first processor operating in the access mode, utilizing the first processor to control a logic value of a busy signal, to indicate that the first processor has permission to access the storage device; in response to a first predetermined condition, controlling the first processor to enter the detection mode from the access mode; in response to a second predetermined condition, controlling the second processor to enter the access mode from the detection mode; and in response to the second processor operating in the access mode, utilizing the second processor to control the logic value of the busy signal, to indicate that the second processor has the permission.