Processor Store Queue Transfer with Anticipatory Cache Requests
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Solution Overview
Problem
Existing processor systems face challenges in improving data transfer performance and reliability between the processor core and processor cache due to synchronization issues in communication protocols and competition for cache store queue entries among multiple threads.
Innovation Solution
Implementing a cache memory system that anticipates available entries, transmits additional acknowledgement signals, and strategically delays requests to optimize data transfers, using cache memory to manage store queues and minimize synchronization losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor core sends data packets to the cache store queue without anticipating available entries, then the communication protocol is simple, but data transfer performance is limited and cache rejections occur
Solution Approach 1:
The cache store queue monitors its own entry availability and proactively sends advance request signals to the processor core before the core actually needs to transfer data. This preliminary action allows the core to prepare data packets in advance, reducing cache rejections and improving transfer performance without requiring complex coordination protocols.
2Productivity
If multiple threads compete for cache store queue entries, then processor utilization is high, but synchronization is lost and data transfer reliability decreases
Solution Approach 1:
The cache store queue continuously monitors its entry availability status and provides feedback through advance request signals to the processor core. This feedback mechanism allows the core to adjust its data transfer timing based on actual cache availability, maintaining synchronization even under high multi-threaded workloads where entry competition occurs.
3Speed
If the cache sends frequent requests for data packets, then data transfer speed increases, but the processor core must wait longer for acknowledgments and synchronization is lost
Solution Approach 1:
The cache sends advance request signals before the processor core actually needs to transfer data, allowing the core to prepare packets in advance. This eliminates the need for the core to wait for frequent requests and acknowledgments, reducing waiting time while maintaining high transfer speed through proactive entry availability indication.
Data Source
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AI summary
A processor includes a load and store unit (LSU) and a cache memory, and transfers data information from a store queue in the LSU to the cache memory. The cache memory requests an information packet from the LSU when the cache memory determines that an available entry exists in a store queue within the cache memory. The LSU acknowledges the request and transfers an information packet to the cache memory. The LSU anticipates that an additional available entry exists in the cache memory, transmits an additional acknowledgement to the cache memory, and transfers an additional information packet, before receiving an additional request from the cache memory. The cache memory stores the additional information packet if an additional available entry exists in the cache store queue. The cache memory rejects the additional information packet if no additional available entries exist in the cache store queue. The LSU must then retry the transfer of the additional information packet when the cache memory subsequently requests the additional information packet. The cache memory can set or reset a time delay in requesting a subsequent information packet based on several factors within the cache memory and the processor, including the number of available entries within the cache store queue. A corresponding method and computer program product are also disclosed.