Processor Subroutine Cache for Low-Power, Stall-Free Execution

Solution Overview

Problem

Repeated access of subroutine instructions from memory increases energy consumption and causes processor pipeline stalls, detrimental to performance.

Innovation Solution

A processor with a subroutine cache that uses register-based subroutine calls and flag multiplexing to identify cached subroutines, reducing circuitry and energy consumption without compromising performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If subroutine instructions are repeatedly accessed from memory, then program size is reduced and organization is improved, but energy consumption increases and processor performance deteriorates

Engineering Contradiction:

Improveprogram sizeVSAvoidenergy consumption

Core Design Contradiction:

Device complexityVSUse of energy by moving object

Solution Approach 1:

The system performs preliminary action by pre-fetching and caching subroutine instructions into a dedicated subroutine cache before they are needed for execution. This allows the instructions to be readily available in fast memory, eliminating repeated slow memory accesses and reducing energy consumption during subroutine execution.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

A subroutine cache is introduced as an intermediary component between main memory and the execution unit. This cache stores frequently accessed subroutine instructions and provides them to the execution unit, reducing the need for repeated full memory accesses and thereby lowering energy consumption.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Device complexity

If subroutine instructions are repeatedly accessed from memory, then program organization is improved, but processor pipeline stalls increase

Engineering Contradiction:

Improveprogram organizationVSAvoidpipeline stall cycles

Core Design Contradiction:

Device complexityVSLoss of time

Solution Approach 1:

The system performs preliminary action by pre-fetching and caching subroutine instructions into a dedicated subroutine cache before they are needed for execution. This allows the instructions to be readily available in fast memory, eliminating repeated slow memory accesses and reducing energy consumption during subroutine execution.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

A subroutine cache is introduced as an intermediary component between main memory and the execution unit. This cache stores frequently accessed subroutine instructions and provides them to the execution unit, reducing the need for repeated full memory accesses and thereby lowering energy consumption.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Speed

If a traditional cache is used to store subroutine instructions, then access speed is improved, but circuitry complexity and power consumption increase

Engineering Contradiction:

Improvesubroutine access speedVSAvoidcircuitry complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The cache system is segmented into a specific subroutine cache that is dedicated to storing only subroutine instructions, separate from the main instruction cache. This segmentation allows for optimized, simpler circuitry tailored specifically for subroutine access patterns, reducing overall circuitry complexity while maintaining high access speed for subroutines.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system applies local quality by creating a specialized subroutine cache with properties optimized specifically for subroutine instructions, rather than using a general-purpose cache. This localized optimization reduces the complexity requirements while maintaining high performance for the specific use case of subroutine execution.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS12455745B2Processor subroutine cache

Publication Date: 2025.10.28 TEXAS INSTRUMENTS INC

AI summary

A processor includes an execution unit and a subroutine cache. The execution unit is configured to execute instructions. The subroutine cache us configured to provide instructions of a subroutine to the execution unit for execution. The subroutine cache includes subroutine instruction storage, a subroutine address register, and subroutine cache control logic. The subroutine control logic is configured to: identify a subroutine call instruction provided to the execution unit; determine whether an instruction of a subroutine invoked by the subroutine call instruction is stored in the subroutine instruction storage by evaluating a subroutine validity indicator that indicates whether at least a portion of the subroutine is stored in the subroutine instruction storage; and provide the instruction of the subroutine to the execution unit based on the subroutine validity indicator indicating that at least a portion of the subroutine is stored in the subroutine instruction storage.