Processor Synchronization via Address Data Comparison
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Solution Overview
Problem
Conventional systems requiring physical redundancy for fault detection in security-critical functions are costly and complex, especially when using custom ASIC designs, and are not suitable for processors not designed for lockstep synchronized operation.
Innovation Solution
A method involving an electronic circuit that synchronizes operations of multiple processors by comparing addresses and data values, using an asynchronous ready signal to ensure synchronization and initiate security measures when discrepancies are detected, without requiring processors to run in exact lockstep.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional lockstep synchronized operation with external verification circuitry is used, then fault detection capability is improved, but device complexity and cost increase significantly
Solution Approach 1:
The invention extracts the verification function from external dedicated circuitry and relocates it within the processor core itself. The verification unit is integrated into the processor, allowing fault detection to be performed internally without requiring separate external verification hardware, thus reducing overall system complexity while maintaining fault detection capability.
Solution Approach 2:
The processor is designed to perform multiple functions: normal computation, self-verification, and fault detection all within the same processing unit. The verification unit can operate in different modes (verification mode and normal mode), allowing the same hardware to serve both computational and verification purposes, eliminating the need for separate dedicated verification circuitry.
2Reliability
If custom ASIC designs are used for redundant processors, then fault detection is improved, but ease of manufacture and upgradeability deteriorate
Solution Approach 1:
The system uses dynamically switchable operational modes that can be changed at runtime. The processor can transition between verification mode and normal mode based on operational requirements, allowing the same hardware to adapt to different functional needs without requiring custom ASIC designs for each mode, thereby improving manufacturing flexibility and upgradeability.
Solution Approach 2:
The invention changes the operational parameters of the processor (verification mode vs. normal mode) rather than requiring different hardware designs. By modifying the operational state and control signals, the system achieves fault detection functionality using standard processor architectures, making them easier to manufacture and upgrade compared to custom ASIC designs.
3Measurement precision
If processors are required to run in exact lockstep, then synchronization accuracy is improved, but productivity and flexibility deteriorate
Solution Approach 1:
The system performs preliminary verification by comparing intermediate results during computation rather than requiring complete lockstep synchronization. The verification unit checks partial results at strategic points, allowing processors to operate more independently while still ensuring accuracy, thus improving productivity without sacrificing synchronization accuracy for critical verification points.
Solution Approach 2:
Instead of requiring complete lockstep synchronization for all operations, the system applies verification selectively to critical computational steps. The verification unit performs partial verification on key intermediate results, which is sufficient to ensure overall accuracy while allowing greater flexibility and efficiency in processor operation compared to strict lockstep requirements.
Data Source
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AI summary
Systems (100) and methods (300) for synchronizing operations of processors (102, 104). The methods involve: receiving by an electronic circuit (106) a first request (250) from a first processor for writing first data (262) to or reading first data from a first address (260) in a first data store (122), and subsequently a second request (252) from a second processor for writing second data (266) to or reading second data from a second address (264) in a second data store (124); comparing values of the first and second addresses to each other and values of the first and second data to each other; and concurrently communicating an asynchronous ready signal (254) from the electronic circuit to the processors when the values of the addresses and data respectively match each other. The asynchronous ready signal causes operations of the processors to be synchronized in time with each other.