Processor Synchronization via Time-Encoded Signal
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Solution Overview
Problem
Conventional processor synchronization methods require multiple signal lines and general-purpose input-output pins, leading to inefficiencies and longer synchronization times.
Innovation Solution
A method where a clock-giving processor sends a signal with alternating edges, where the temporal distance between edges encodes the counter state, allowing simultaneous transmission of start times and synchronization confirmation, reducing the need for additional signal lines and pins through time-division multiplexing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple signal lines are used for processor synchronization, then synchronization reliability is improved, but device complexity and pin usage increase
Solution Approach 1:
The patent combines multiple synchronization signals (counter state indication and process start time indication) into a single signal line. The clock-giving processor transmits both the current counter state and the process start time information through one unified signal, eliminating the need for separate signal lines and reducing overall system complexity while maintaining synchronization reliability.
Solution Approach 2:
The signal line is designed to serve multiple functions simultaneously. It transmits both counter state information and process start time information, making a single signal line universal for multiple synchronization purposes. This multi-functionality reduces the total number of signal lines and pins required in the system.
2Measurement precision
If multiple signal lines are used for processor synchronization, then synchronization accuracy is improved, but the number of pins required increases
Solution Approach 1:
The patent merges multiple synchronization data streams into a single signal transmission channel. By encoding both counter state and process start time information in one signal, the system reduces pin quantity from multiple dedicated pins to a single shared pin, while preserving synchronization accuracy through comprehensive information transmission.
3Loss of information
If separate signals are used for counter state and start time, then information clarity is improved, but signal line usage increases
Solution Approach 1:
The patent segments information transmission into two sequential phases within a single signal line: first transmitting the counter state information, then transmitting the process start time information. This temporal segmentation maintains information clarity by preventing data confusion, while the spatial consolidation into one signal line reduces overall system complexity.
Solution Approach 2:
The synchronization signal operates periodically, first indicating the counter state and then indicating the process start time in a repeating cycle. This periodic structure ensures clear information transmission by establishing predictable timing patterns, while using a single signal line reduces device complexity compared to parallel signal lines.
Data Source
AI summary
A method and device for the synchronization of processes, a first signal being sent by a clock-giving processor, the first signal having, in an alternating manner, first edges having a first direction and second edges having a second direction opposite the first edge, a temporal distance between at least one of the first edges and at least one of the second edges being determined as a function of a state of a counter in the clock-giving processor. A method for the synchronization of processes, a first signal being received by a clock-receiving processor, the first signal having, in an alternating manner, first edges having a first direction and second edges having a second direction opposite the first edge, a state of a counter in the clock-receiving processor being determined as a function of a temporal distance between at least one of the first edges and at least one of the second edges.