Processor Synchronization via Timestamp Exchange
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Solution Overview
Problem
Existing synchronization methods between multiple processors in electronic devices face challenges due to signal delay and counting errors caused by different clock sources, leading to potential system crashes or hangs.
Innovation Solution
A method where a first processor periodically sends its count value to a second processor through a communication interface, with the second processor adding a preset deviation value to synchronize its count value, eliminating signal delay and counting errors by resetting and accumulating values to maintain synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the master processor sends its processor clock signal directly to the slave processor through one wire, then the device complexity is reduced, but the measurement precision of time stamp count values deteriorates due to signal delay
Solution Approach 1:
The patent introduces a communication interface as an intermediary between processors. Instead of directly transmitting clock signals through wires, processors exchange time stamp count values through the communication interface, which handles the data transfer and synchronization protocol, thereby avoiding signal delay issues while maintaining system complexity at an acceptable level
Solution Approach 2:
The patent replaces the mechanical/electrical direct clock signal transmission method with a software-based time stamp exchange mechanism. Rather than physically synchronizing clocks through wire-connected signal transmission, the system uses digital communication to exchange count values and perform software-based synchronization, substituting physical signal transmission with data processing
2Device complexity
If processors with different clock sources operate at the same frequency, then the device complexity is reduced, but the reliability of program execution deteriorates due to count value differences causing interruptions or crashes
Solution Approach 1:
The patent implements a feedback mechanism where processors periodically exchange time stamp count values through the communication interface. The slave processor receives the master's count value, compares it with its own, and adjusts its counting accordingly. This continuous feedback loop ensures count value consistency across processors with different clock sources, maintaining program execution reliability
Solution Approach 2:
The patent changes the synchronization approach from frequency-based to parameter-based synchronization. Instead of relying on identical clock frequencies, the system uses time stamp count values as the synchronization parameter. By exchanging and comparing these parameter values, the system achieves reliable synchronization even when underlying clock parameters (sources, frequencies) differ
Data Source
AI summary
An electronic device comprises a first processor, a second processor and a communication interface. The first processor operates according to a first clock, and comprises a first time-stamp counter to count the first clock to obtain a first count value. The second processor operates according to a second clock, and comprises a second time-stamp counter to count the second clock to obtain a second count value. The communication interface is coupled between the first processor and the second processor. The first processor periodically sends the first count value to the second processor through the communication interface. When the second processor receives the first count value, the second processor adds a preset deviation value to the first count value to obtain a synchronization value, resets the second count value, and the sum of the synchronization value and the second count value is read by the second processor.