Processor Table Lookup Unit Parallel Vector Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As digital signal processing algorithms become more complex, existing coprocessors face challenges in power efficiency due to the need for numerous processing passes and less regular access patterns, compromising their performance and efficiency.
Innovation Solution
A processor design incorporating a scalar processor core and a vector coprocessor core that processes instructions and data in parallel, featuring a register file, execution units, and specialized units for table lookup and histogram updates, enabling efficient execution of complex processing tasks with improved power and area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If coprocessors are used to accelerate processing tasks, then processing performance is improved, but power efficiency deteriorates due to numerous processing passes
Solution Approach 1:
The processor is divided into two specialized cores: a scalar processor core for control and sequential operations, and a vector processor core for parallel data processing. This segmentation allows each core to be optimized for its specific function, enabling the vector core to handle complex signal processing tasks in fewer passes while the scalar core manages control flow, thereby improving both performance and power efficiency.
Solution Approach 2:
The vector processor core is designed with multiple execution units that can handle various digital signal processing operations (scaling, filtering, transformation, sum of absolute differences) within a single processing pass. This multi-functionality eliminates the need for multiple specialized coprocessors and numerous processing passes, reducing power consumption while maintaining high productivity.
2Productivity
If coprocessors are designed to accommodate regular access patterns, then processing efficiency is improved, but adaptability to less regular access patterns deteriorates
Solution Approach 1:
The vector processor core employs dynamic execution units that can adapt their operation based on the specific access patterns required by the algorithm. The execution units are configured to handle both regular and irregular access patterns efficiently, allowing the processor to maintain high efficiency across diverse workloads without being constrained to a single access pattern type.
Solution Approach 2:
The processor allows configuration of execution unit parameters to match the specific requirements of different algorithms. By changing parameters such as data width, access stride, and processing depth, the vector core can optimize its performance for various access patterns, from highly regular to irregular patterns, thereby maintaining both efficiency and adaptability.
Data Source
AI summary
A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage, and pass vector instructions in the instruction stream to the vector coprocessor core. The vector coprocessor core includes a register file, a plurality of execution units, and a table lookup unit. The register file includes a plurality of registers. The execution units are arranged in parallel to process a plurality of data values. The execution units are coupled to the register file. The table lookup unit is coupled to the register file in parallel with the execution units. The table lookup unit is configured to retrieve table values from one or more lookup tables stored in memory by executing table lookup vector instructions in a table lookup loop.