Processor Telemetry Accumulators for Power Management
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Solution Overview
Problem
The increasing power requirements and energy consumption of multicore processors pose a significant challenge for energy efficiency in computing systems, as they contribute substantially to overall electricity usage, necessitating innovative power management solutions to balance performance with reduced energy consumption.
Innovation Solution
The implementation of integrated voltage regulators (IVRs) and power control units (PCUs) within multicore processors allows for fine-grained control of voltage and power distribution across cores, enabling independent operation and dynamic power management through techniques like dynamic voltage frequency scaling, workload swapping, and hardware duty cycling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple cores and hardware threads are integrated on a single integrated circuit to increase computing density, then processing capability and functionality are improved, but power requirements and energy consumption escalate
Solution Approach 1:
The processor is divided into multiple independent cores (first core, second core, etc.) that can be individually managed. Each core has its own performance state controls, allowing selective activation and independent power management. This segmentation enables the system to activate only the necessary number of cores based on workload, reducing overall power consumption while maintaining processing capability.
Solution Approach 2:
The system implements dynamic performance states (performance enable states and performance disable states) that can be transitioned between based on computational workload. The performance controller dynamically adjusts which cores are active and at what performance level, allowing the processor to adapt its power consumption to actual computational needs rather than operating at maximum capacity continuously.
2Use of energy by moving object
If dynamic voltage frequency scaling and fine-grained power control are implemented across multiple cores, then energy efficiency is improved, but device complexity increases
Solution Approach 1:
The performance controller is designed as a universal management unit that handles multiple functions: it controls performance states for multiple different cores, manages transitions between enable and disable states, and coordinates with voltage regulators. This multi-functional approach consolidates what could be multiple separate control mechanisms into a single versatile controller, managing complexity while enabling fine-grained power control across the processor.
Solution Approach 2:
The performance controller acts as an intermediary between the cores and the voltage regulators. Rather than having direct complex control mechanisms in each core, the performance controller mediates by receiving workload information and translating it into coordinated performance state changes and voltage adjustments, simplifying the overall control architecture while achieving fine-grained power management.
Data Source
AI summary
In an embodiment, a processor includes a plurality of cores including a first core. The first core includes a first plurality of accumulator logics, each accumulator logic of the first plurality of accumulator logics to store corresponding first core telemetry data. The processor also includes a power management unit (PMU) to request telemetry data from the first core and in response to receive the first core telemetry data stored in at least one accumulator logic of the first plurality of accumulator logics. Other embodiments are described and claimed.