Processor Test Case Shuffling for Verification Coverage

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Solution Overview

Problem

The existing processor testing tools require a large amount of upfront time to generate numerous test cases, leaving insufficient time for actual processor testing due to the inefficiency in generating test cases that provide maximum coverage and stress various timing scenarios.

Innovation Solution

A system and method that creates multiple test case scenarios from one test case by shuffling the instruction order while maintaining relative sub-test case instruction order intact, allowing for efficient processor testing by reusing the same test case and reshuffling its instructions, thereby reducing the time spent on generating new test cases.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple test cases are generated to sufficiently test the processor, then test coverage is improved, but time consumption for generating test cases increases

Engineering Contradiction:
Improvetest coverageVSAvoidtime for generating test cases
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent creates multiple test case scenarios by copying a single base test case and shuffling its instruction order. Instead of generating entirely new test cases, the system reuses the same test case structure with different instruction sequences, thereby maintaining test coverage while significantly reducing the time required to create multiple test scenarios.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent introduces dynamic shuffling of instruction order within test cases. By dynamically reordering instructions while maintaining relative sub-test case instruction order, the system generates diverse test scenarios from a single base test case, improving test coverage without proportionally increasing generation time.

Inventive Principle:
Principle #15Dynamics

2Loss of time

If test case generation time is reduced, then time for processor testing increases, but test case diversity may be compromised

Engineering Contradiction:
Improvetime for generating test casesVSAvoidtest case diversity
Core Design Contradiction:
Loss of timeVSAdaptability or versatility

Solution Approach 1:

The patent segments test cases into sub-test cases with specific instruction orders. By dividing the test case structure into manageable segments and shuffling only the order between segments rather than individual instructions, the system maintains test case diversity while enabling efficient generation through structured recombination.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary organization of instructions into sub-test cases with defined instruction orders. This preliminary structuring allows for efficient shuffling in subsequent steps, as the system only needs to reorder pre-validated segments rather than generating entirely new test cases from scratch.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7669083B2System and method for re-shuffling test case instruction orders for processor design verification and validation
Publication Date: 2010.02.23 X CORP
  • US7669083B2 patent drawing
  • US7669083B2 patent drawing
  • US7669083B2 patent drawing

AI summary

A system and method for creating multiple test case scenarios from one test case by shuffling the test case instruction order while maintaining relative sub test case instruction order intact is presented. A test case generator generates and provides a test case that includes multiple sub test cases to a test case executor. In turn, the test case executor recursively schedules and dispatches the test case with different shuffled instruction orders to a processor in order to efficiently test the processor. In one embodiment, the test case generator provides multiple test cases to the test case executor. In another embodiment, the test case generator provides test cases to multiple test case executors that, in turn, shuffle the test cases and provide the shuffled test cases to their respective processor.