Processor Test Pattern Re-execution for Timing Scenario Coverage
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Solution Overview
Problem
The test pattern build stage in processor verification is the most time-consuming process, overshadowing the test pattern execution and validation/verification stages, resulting in insufficient time for these critical phases.
Innovation Solution
Re-executing test patterns in varying timing scenarios by varying the initial cache line memory states, which reduces test pattern build time and increases system test coverage, while ensuring the same final state of memory and processor registers for simplified error checking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test patterns are rebuilt for each verification run, then test coverage can be maximized, but test pattern build time increases significantly
Solution Approach 1:
The system performs preliminary actions by varying initial cache line memory states before test pattern execution. By pre-configuring different cache states (hit, miss, partial hit) for test pattern re-execution, the system eliminates the need to rebuild test patterns while still achieving diverse timing scenario coverage. This preliminary state preparation allows the same test pattern to be reused multiple times with different initial conditions.
Solution Approach 2:
The system changes parameters by varying initial cache memory states rather than changing the test pattern code itself. By modifying the initial state parameters of cache lines (present, absent, partial presence), the system creates different timing scenarios during test pattern re-execution, achieving diverse verification coverage without requiring new test pattern generation.
2Reliability
If more time is allocated to test pattern execution and validation, then verification quality improves, but test pattern build time must be reduced
Solution Approach 1:
The system uses copying by re-executing the same test pattern multiple times with different initial cache states. Instead of creating new test patterns for each verification scenario, the system copies and reuses the original test pattern with modified initial memory states, significantly reducing build time while maintaining comprehensive verification coverage.
3Reliability
If test patterns are re-executed with varying initial cache states, then timing scenario coverage increases, but test pattern execution complexity increases
Solution Approach 1:
The system applies segmentation by dividing the verification process into distinct phases: initial cache state configuration, test pattern execution, and result validation. By segmenting the control of initial cache states from the test pattern execution itself, the system manages complexity through modular organization while achieving comprehensive timing scenario coverage.
Data Source
AI summary
A system and method processor testing using test pattern re-execution is presented. A processor re-executes test patterns using different timing scenarios in order to reduce test pattern build time and increase system test coverage. The invention described herein varies initial states of a processor's memory (cache, TLB, SLB, etc.) that, in turn, varies the timing scenarios when re-executing test patterns. By re-executing the test patterns instead of rebuilding new test patterns, verification quality is improved since more time is available for execution, verification and validation. In addition, since the test patterns result in the same final state, the invention described herein also simplifies error checking.