Processor Thread Scheduler Event Response
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current processor designs face challenges in efficiently handling increasing numbers of communications, particularly in mobile applications, due to limitations in interrupt handling and polling methods, which result in delayed reaction times and high power consumption when using FPGAs or ASICs.
Innovation Solution
A processor with a thread scheduler that manages runnable and suspended threads using specific instructions to quickly respond to events, decoupling event setup from thread suspension, allowing for flexible configuration and efficient resource management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If interrupt handling is used to respond to peripheral device activity, then the processor can react to events, but the current program state must be saved before the interrupt can be acted upon, introducing delay
Solution Approach 1:
The processor pre-positions thread context information (program counter, registers, stack pointer) in dedicated thread control blocks before events occur. When an event happens, the thread can resume immediately from the saved context without requiring state save/restore operations, thus eliminating interrupt handling delays while maintaining fast response capability
2Adaptability or versatility
If FPGAs are used to achieve configurability for different applications, then the processor can be tailored to specific needs, but they are more expensive, slower and consume more power than ASICs
Solution Approach 1:
The processor architecture segments the interface control functionality into separate programmable threads that can be dynamically loaded and unloaded. This allows the processor to configure specific interface handling routines as needed rather than having all interface logic permanently implemented in reconfigurable logic, reducing power consumption while maintaining adaptability through software-based reconfiguration
Solution Approach 2:
The patent replaces hardware-based reconfigurability (FPGA) with software-based thread scheduling and context switching. The programmable interface controllers use instruction sets and thread management to achieve reconfiguration, substituting mechanical/electrical reconfigurable logic with software control, thereby reducing power consumption while maintaining versatility
3Reliability
If polling is used to check device readiness, then the processor can determine device state, but it introduces delayed reaction time and is slow due to continual queries and responses
Solution Approach 1:
The processor employs event-driven mechanisms where peripheral devices automatically generate events when ready, and the thread scheduler autonomously manages thread suspension and resumption based on event occurrence. This self-service approach eliminates the need for continuous polling queries, allowing reliable device state monitoring without the speed penalty of continual checking
Data Source
Figure 1
Figure 2
Figure 2A
AI summary
The invention provides a processor comprising: an execution unit, and a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a respective runnable status for each thread. The execution unit is configured to execute thread scheduling instructions which manage the runnable statuses. The thread scheduling instructions including at least: one or more source event enable instructions each of which sets an event source to a mode in which it generates an event dependent on activity occurring at that source, and a wait instruction which sets one of said runnable statuses to suspended pending one of the events upon which continued execution of the respective thread depends. The continued execution comprises retrieval of a continuation point vector for the respective thread.