Processor Thread Scheduling via Atomic Bit String Rotation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multiprocessor systems, the communication between the management unit and processors for thread scheduling often causes message delays and interrupt issues, leading to reduced system efficiency and instability, especially when interrupts are disabled or not disabled during scheduling.
Innovation Solution
Assigning identifiers to execution units, retaining executable-or-not and last executed information, and selecting executable units based on these identifiers using atomic operations, allowing processors to select and update thread information without locking the task queue, thus avoiding interrupt-related inefficiencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interrupts are not disabled during scheduling, then interrupt response is maintained, but scheduling cannot be performed until interrupt processing ends and the task queue is unlocked, resulting in reduced system efficiency
Solution Approach 1:
The patent segments the scheduling operation into two independent parts: (1) reading thread information from the task queue, and (2) selecting and updating the next thread to execute. By separating these operations, the processor can read thread information without disabling interrupts, then perform the selection and update atomically. This resolves the contradiction by allowing interrupt handling to proceed while still enabling efficient scheduling updates.
Solution Approach 2:
The patent performs preliminary actions by having the processor read and prepare thread information from the task queue before executing the atomic selection and update operation. This preliminary reading phase can occur with interrupts enabled, and only the critical update portion requires atomic operations, thus maintaining interrupt response while ensuring scheduling efficiency.
2Stability of the object's composition
If interrupts are disabled during scheduling, then system stability is improved, but the system drops in interrupt response
Solution Approach 1:
The scheduling process is segmented into a non-critical reading phase (with interrupts enabled) and a critical update phase (with atomic operations). This segmentation maintains system stability during the atomic update while avoiding unnecessary interrupt disabling during the reading phase, thus preventing interrupt response delays.
Solution Approach 2:
The patent replaces the traditional mechanical approach of disabling/enabling interrupts with a software-based atomic operation mechanism. Instead of using hardware interrupt control, the system uses atomic read-modify-write operations to ensure thread-safe updates without affecting interrupt handling, thus maintaining both stability and responsiveness.
3Stability of the object's composition
If the task queue is locked during scheduling, then data consistency is ensured, but processing speed is reduced due to the locking overhead
Solution Approach 1:
The patent substitutes the mechanical locking mechanism with atomic memory operations. Instead of acquiring and releasing locks on the task queue, the processor uses atomic read-modify-write operations to update thread information. This eliminates locking overhead while ensuring data consistency through the atomic nature of the operations.
Solution Approach 2:
The patent implements a copy-then-update pattern where the processor reads thread information from the task queue, performs the selection locally, and then atomically updates the result. This copying approach allows the majority of the scheduling logic to execute without blocking other processors, with only the final update requiring atomic operations to maintain data consistency.
4Adaptability or versatility
If a kernel thread is preempted while the user-level scheduler is running, then multitasking is maintained, but the user-level schedulers on other processors cannot perform scheduling until the lock is released
Solution Approach 1:
The patent segments the scheduling operation so that the critical section (atomic update) is minimized. By separating the thread information reading (which can be preempted) from the atomic update operation, other processors can perform their scheduling updates independently without being blocked by preemptions on one processor, thus maintaining both multitasking and high scheduling throughput.
Solution Approach 2:
Each processor independently performs its own scheduling operations using atomic updates without requiring coordination or locking with other processors. This self-service approach allows preempted threads on one processor to not affect the scheduling capability of other processors, maintaining system-wide scheduling throughput while preserving multitasking preemption capabilities.
Data Source
AI summary
Thread information is retained in a main memory. The thread information includes a bit string and last executed information. Each bit of the bit string is allocated to a thread, and the number and the value of the bit indicate the number of the thread and whether or not the thread is in an executable state, respectively. The last executed information is the number of a last executed thread. A processor rotates the bit string so that a bit indicating the last executed thread comes to the end of the bit string. It searches the rotated bit string for a bit corresponding to a thread in the executable state in succession from the top, and selects the number of the first obtained bit as the number of the next thread to be executed. Then, the thread information is updated by changing the value of the bit of this number to indicate not being executable, and setting the last executed information to the number of this bit. This operation is performed by using an atomic command.