Processor Thread Scheduling via Dynamic Activity Vectors
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Solution Overview
Problem
In multi-threaded processors, ensuring predictable performance for individual threads is challenging due to resource competition, particularly during simultaneous memory access operations or input-output operations, leading to potential delays and inefficiencies.
Innovation Solution
A processor architecture with a thread scheduler that uses continuation point vectors to manage thread execution, allowing for dynamic scheduling based on activity, and enabling threads to share resources while ensuring each thread receives processor cycles, thereby preventing delays and optimizing resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If processor cycles are reserved for each thread, then each thread can progress without delay, but resources are wasted on threads that have nothing to do
Solution Approach 1:
The system dynamically allocates memory access ports to threads based on actual demand rather than static reservation. The thread scheduler monitors thread activity and grants access to memory ports only when threads have instructions to execute, allowing the system to adapt resource allocation in real-time and avoid wasting resources on idle threads.
Solution Approach 2:
Threads compete for memory access ports based on their own readiness to execute instructions. The scheduling mechanism allows threads to self-manage their resource usage by attempting to access memory ports when ready, with the system automatically arbitrating conflicts without requiring pre-reserved resources for each thread.
2Productivity
If instruction fetches are prioritised, then instruction queues are kept full, but data access may be stalled
Solution Approach 1:
The system implements dynamic prioritization where the importance of instruction fetches versus data accesses changes based on system state. When instruction queues are empty, data accesses receive higher priority. When instruction queues need filling, instruction fetches are prioritized. This dynamic adjustment eliminates the need for static prioritization schemes that cause stalls.
Solution Approach 2:
The scheduling algorithm changes the priority parameter of different thread types based on current system conditions. Instruction fetch threads and data access threads have their priority levels adjusted dynamically according to queue depths and system state, allowing optimal resource allocation without stalling either operation.
3Productivity
If data accesses are prioritised, then data queues are kept full, but instruction fetch may be delayed
Solution Approach 1:
The system dynamically adjusts the priority of data access versus instruction fetch operations based on real-time monitoring of queue depths and thread readiness. This prevents the need for static prioritization that would cause instruction fetch delays, as the system automatically balances between maintaining full data queues and ensuring instruction availability.
4Productivity
If more memory access ports are provided, then resource utilization improves, but device complexity and cost increase
Solution Approach 1:
Instead of providing excessive memory access ports that would increase complexity, the system uses partial action by dynamically allocating a limited number of ports to threads based on actual need. The scheduling mechanism ensures that threads receive memory access capability when required, achieving high resource utilization with a smaller, more manageable number of physical ports.
Data Source
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AI summary
The invention provides a processor for executing threads, each thread comprising a sequence of instructions, said instructions defining operations and at least some of those instructions defining a memory access operation. The processor comprises: a plurality of instruction buffers, each for holding at least one instruction of a thread associated with that buffer; an instruction issue stage for issuing instructions from the instruction buffers; and a memory access stage connected to a memory and arranged to receive instructions issued by the instruction issue stage. The memory access stage comprises: detecting logic adapted to detect whether a memory access operation is defined in each issued instruction; and instruction fetch logic adapted to instigate an instruction fetch to fetch an instruction of a thread when no memory access operation is detected.