Processor Thread Scheduling Based on Stall Characteristics
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Solution Overview
Problem
Computer processors face inefficiencies in thread scheduling, leading to performance bottlenecks and increased power consumption due to oversaturation or starvation of datapath units, particularly in graphics processing units (GPUs) where threads are mapped to execution resources in a manner that does not account for varying instruction latencies and cache misses.
Innovation Solution
A two-stage scheduling technique is implemented, where the first stage assigns threads to channels based on compiler hints and back-pressure information, and the second stage assigns instructions from channels to execution pipelines, allowing for dynamic adjustment of thread priority and channel deactivation to prevent stalls and optimize resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If threads are mapped to execution resources in a conventional manner, then the processor can execute multiple threads, but performance bottlenecks and increased power consumption occur due to oversaturation or starvation of datapath units
Solution Approach 1:
The patent implements dynamic thread scheduling that adjusts thread priority and execution mapping based on real-time pipeline stall characteristics and execution resource availability. The scheduler monitors stall events and dynamically reassigns threads to prevent both oversaturation and starvation of datapath units, optimizing power consumption while maintaining productivity
Solution Approach 2:
The system incorporates feedback mechanisms that monitor pipeline stall characteristics and execution resource utilization. This feedback information is used to adjust scheduling decisions, ensuring that threads are mapped to execution resources in a manner that prevents both oversaturation and starvation, thereby reducing power consumption while maintaining high productivity
2Device complexity
If threads are mapped to execution resources without accounting for varying instruction latencies, then scheduling is simpler, but performance bottlenecks occur due to pipeline stalls
Solution Approach 1:
The patent implements preliminary detection of pipeline stall characteristics before threads are mapped to execution resources. By identifying potential stall conditions in advance, the scheduler can proactively adjust thread mapping to prevent performance bottlenecks, balancing the complexity of the scheduling mechanism with pipeline execution efficiency
3Area of stationary object
If all threads are continuously scheduled to execution pipelines, then maximum resource utilization is achieved, but chip area increases due to need for handling all thread states
Solution Approach 1:
The patent implements a channel deactivation mechanism that discards (deactivates) threads from execution pipelines when they are likely to cause long stalls. These threads are recovered and reactivated when pipeline conditions improve, allowing the system to maintain high resource utilization while reducing chip area requirements for handling all thread states simultaneously
Data Source
AI summary
Techniques are disclosed relating to channel stalls or deactivations based on the latency of prior operations. In some embodiments, a processor includes a plurality of channel pipelines for a plurality of channels and a plurality of execution pipelines shared by the channel pipelines and configured to perform different types of operations provided by the channel pipelines. First scheduler circuitry may assign threads to channels and second scheduler circuitry may assign an operation from a given channel to a given execution pipeline based on decode of an operation for that channel. Dependency circuitry may, for a first operation that depends on a prior operation that uses one of the execution pipelines, determine, based on status information for the prior operation from the one of the execution pipelines, whether to stall the first operation or to deactivate a thread that includes the first operation from its assigned channel.