Processor Tile Voltage Regulation With Fast Droop Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing power control systems for large digital logic circuits, such as microprocessors, face inefficiencies and increased overhead due to high-frequency switching and complex analog design blocks, which lead to significant power consumption and IC real estate usage in responding to transient loading conditions and voltage droops.
Innovation Solution
A processor system employing a dual-regulation loop architecture, where a digital low-dropout controller and a fast droop detector work in tandem to regulate supply voltages, using digital and analog circuits respectively, to efficiently manage voltage droops by selectively activating transistors and adjusting resistive elements, thereby reducing power consumption and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If header circuits constantly switch at high frequency above 1 GHz to respond to transient loading conditions, then voltage droop response speed is improved, but power consumption and device complexity increase significantly
Solution Approach 1:
The system dynamically adjusts the switching frequency of header circuits based on operating conditions. During transient loading conditions, the frequency increases to above 1 GHz for fast response, while during steady-state operation, the frequency reduces to minimize power consumption. This dynamic frequency adjustment resolves the contradiction between fast response and low power consumption.
Solution Approach 2:
The header circuits operate with periodic switching rather than continuous switching. By enabling the header circuits only when needed (during transient conditions) and disabling them during steady-state operation, the system achieves fast response when necessary while significantly reducing average power consumption and device complexity.
2Reliability
If header circuits constantly switch at high frequency to respond to transient loading conditions, then voltage regulation performance is improved, but IC real estate usage increases
Solution Approach 1:
The system dynamically configures the header circuit structure based on operating conditions. During transient loading, the header circuits are enabled with full functionality for optimal voltage regulation. During steady-state operation, the header circuits are disabled or configured in a low-overhead mode, reducing the effective IC real estate required while maintaining voltage regulation performance when needed.
Solution Approach 2:
The header circuits are designed to serve multiple functions: fast transient response, steady-state voltage regulation, and power management. By integrating these functions into a single reconfigurable structure, the system achieves high voltage regulation performance without requiring separate dedicated circuits for each function, thereby reducing overall IC real estate usage.
3Speed
If header circuits are optimized to respond very quickly to voltage droops, then transient response performance is improved, but device complexity and power consumption increase
Solution Approach 1:
The voltage regulation system is segmented into multiple hierarchical levels: fast-responding header circuits for transient conditions, medium-responding voltage regulators for steady-state operation, and slow-responding power management units for overall power optimization. This segmentation allows each component to be optimized for its specific function, achieving fast transient response without requiring the entire system to be complex and high-power.
Solution Approach 2:
The header circuits act as intermediaries between the power supply and the load, providing fast transient response while isolating the complexity from the rest of the system. By placing the header circuits close to the load and using them as a first line of defense against voltage droops, the system achieves fast response without propagating complexity throughout the entire power management architecture.
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
A processor system includes first and second regulators for regulating an adjusted supply voltage. The first and second regulators generate a plurality of control signals to regulate an adjusted power supply voltage and that generate a charge when a droop level falls below a droop threshold value by implementing first and second control loops. A supply adjustment block with the two regulators and control loops are provided for each processor core allowing different cores to have different regulated supply levels all based on one common supply. One regulator is a global regulator while another is a local regulator found in each of the processing tiles. Processing tiles are grouped into two groups wherein one group includes tiles that may powered down to save power. Voltage rails of the two groups are selectively connected to equalize voltage levels when both groups are powered on and operating.