Processor Tiny Register Files for Faster, Lower-Power Operand Access
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Solution Overview
Problem
High dynamic power consumption in GPU/GPGPU chips due to frequent read and write access to general-purpose register files, exacerbated by the increasing number of registers, which affects computation performance.
Innovation Solution
Implementing a processor with a set of register files and tiny register files, connected by an operand collector, allowing direct operand access from tiny register files to reduce read-write times and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of general-purpose registers is increased to support more physical threads and higher computation performance, then the computation capability is improved, but the dynamic power consumption increases significantly
Solution Approach 1:
The patent divides the register file into two segments: a first register file for storing thread data and a second register file (tiny register file) for temporarily storing operands. This segmentation allows the system to use the smaller, lower-power second register file for frequent operand access while maintaining the full capability of the first register file for thread management, thereby reducing overall power consumption while preserving computation capability.
Solution Approach 2:
The patent introduces a second register file as an intermediary between the first register file and the computation units. This intermediary temporarily stores operands needed for computation, reducing the need for frequent accesses to the larger first register file. The intermediary layer thus mediates between the full register capacity and power consumption requirements, achieving a balance between performance and energy efficiency.
2Productivity
If the number of general-purpose registers is increased to support more physical threads, then the instruction execution capability is improved, but the read-write times to the register file increase
Solution Approach 1:
The patent applies preliminary action by pre-loading operands into the second register file (tiny register file) before they are needed for computation. The operand collector collects operands from the first register file and stores them in advance in the second register file, so that computation units can quickly access them without waiting for slower reads from the first register file, thus reducing read-write times and improving instruction execution capability.
Solution Approach 2:
The second register file acts as an intermediary buffer that reduces the time penalty of accessing the larger first register file. By placing frequently accessed operands in the smaller, faster second register file, the system mediates between the large storage capacity and fast access requirements, significantly reducing read-write times while maintaining full thread support capability.
3Adaptability or versatility
If the first register file is made larger to support more physical threads, then the number of supported threads is improved, but the area occupied by the register file increases
Solution Approach 1:
The patent segments the register storage function between two files: the first register file maintains full thread support capability while the second register file (tiny register file) provides additional operand storage with minimal area overhead. This segmentation allows the system to support more physical threads through the coordinated operation of both files without proportionally increasing the total register file area, as the second file uses a more area-efficient storage structure.
Solution Approach 2:
The patent changes the storage structure parameter from conventional SRAM for both files to a different structure (e.g., D-latch based) for the second register file. This parameter change enables the second file to achieve the same storage function with reduced area, allowing the system to support more threads through the combined capacity of both files while controlling the total area occupation.
Data Source
AI summary
The invention discloses a processor and a method for executing an instruction with a processor. The processor comprises a set of tiny register files, each of which is connected correspondingly to one of the set of register files and is configured to temporarily store the operand and the output result of the instruction executed by the plurality of physical threads; and an operand collector, which is connected to the set of register files and to the set of tiny register files and is configured to read the operand of the instruction executed by the plurality of physical threads from the set of register files and/or from the set of tiny register files and write the output result of the instruction executed by the plurality of physical threads to the set of register files and/or to the set of tiny register files. The embodiment of the application can significantly reduce reading and writing times of the register files when the instructions are executed with the processor and reduce dynamic power consumption of the processing chip while boosting the computation speed of the processor.