Processor Trace Data Handling for Recursive Jumps
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Solution Overview
Problem
Existing methods for handling trace data, such as supervisory functions monitoring processor operations, face inefficiencies due to high memory requirements when dealing with nested jumps and subroutine calls, particularly in recursive algorithms, and rely on assumptions that may not always hold, leading to potential data loss or overflow.
Innovation Solution
A processor supervisory unit that stores expected return locations or increments counters for jumps, allowing efficient logging and reporting by comparing actual return locations with expected ones, with mechanisms to manage memory usage and handle recursive jumps effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the supervisory function stores all expected return addresses for nested jumps, then accurate trace data can be collected, but memory requirements increase significantly
Solution Approach 1:
The patent segments the trace data into two parts: (1) a compact representation of expected return addresses using a limited set of stored values, and (2) a counter indicating the number of unmatched jumps. This segmentation allows accurate tracking of program flow while using minimal memory resources.
Solution Approach 2:
Instead of storing complete information about all expected return addresses, the patent uses partial information - storing only a limited set of return address values and using a counter to represent the rest. This partial action approach maintains reliability while reducing memory requirements.
2Loss of information
If the supervisory function logs every jump and return, then complete program flow information is captured, but data volume becomes unmanageably large
Solution Approach 1:
The patent merges multiple pieces of information into a compact format by combining the return address value with a counter that represents the number of unmatched jumps. This merging reduces data volume while preserving the essential program flow information needed for accurate tracing.
Solution Approach 2:
Instead of copying and storing complete jump/return sequences, the patent uses a simplified copy mechanism where only the return address and a counter are stored. This allows the system to represent complex program flow patterns with minimal data while maintaining information completeness.
3Device complexity
If the supervisory function assumes normal return behavior, then data collection is simplified, but accuracy decreases when exceptions occur
Solution Approach 1:
The patent introduces dynamic adaptability by using a counter that can be incremented when jumps are detected and decremented when returns are detected. This dynamic mechanism allows the system to automatically adjust to both normal and exceptional program flow patterns without increasing complexity, maintaining reliability while keeping the system simple.
Data Source
AI summary
A processor supervisory unit for monitoring the program flow executed by a processor, the supervisory unit being arranged to store a set of values representing locations to which the program flow is expected to return after jumps in the program flow, the unit being capable of: in a first mode, on detecting a jump in the program flow to store a location value representing a location to which the program flow is expected to return from that jump; and in a second mode, on detecting a jump in the program flow to increment a counter associated with a location value representing a location to which the program flow is expected to return from that jump.