Processor Trace Messages Using Instruction and Stall Counts
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Solution Overview
Problem
The integration of multiple core devices onto a single System-on-Chip (SoC) reduces the ability of external monitoring tools to effectively monitor instruction execution for security breaches, bugs, and safety concerns due to reduced access and increased data transport, limiting the temporal detail of trace data.
Innovation Solution
A method and architecture for tracing instruction execution on an integrated circuit chip in real-time, using tracing circuitry to count instructions and stall cycles, generating trace messages, and outputting them, with optional threshold comparison and encoding for efficient data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple core devices are integrated onto a single SoC chip, then device integration and compactness are improved, but the ability of external monitoring tools to monitor instruction execution deteriorates due to reduced access and increased data transport
Solution Approach 1:
The patent introduces an on-chip trace buffer as an intermediary component that captures instruction execution data internally within the SoC. This trace buffer acts as a mediator between the processor cores and external monitoring tools, storing trace data locally so that external tools can access detailed execution information without needing direct real-time access to the internal buses, thereby resolving the contradiction between integration and monitoring capability.
2Measurement precision
If detailed trace data is captured for security and debugging purposes, then monitoring precision is improved, but the quantity of data to be transported increases, further reducing monitoring effectiveness
Solution Approach 1:
The patent extracts only the most critical trace information (instruction address, branch taken/not taken) into compact trace messages stored in the on-chip trace buffer. By taking out only the essential debugging and security-relevant data rather than capturing all possible execution details, the system achieves high monitoring precision while minimizing the volume of data that needs to be transported externally.
3Ease of operation
If external monitoring tools are used to monitor SoC execution, then access to core devices is improved, but the temporal detail of trace data deteriorates due to reduced access and increased data transport
Solution Approach 1:
The patent implements preliminary action by capturing and storing trace data in the on-chip trace buffer during processor execution, before any external analysis is performed. The trace buffer pre-captures instruction addresses and branch information in real-time, preserving temporal details of execution flows. This preliminary capture allows external monitoring tools to later analyze the stored trace data without losing temporal information, even though external access occurs after execution.
Data Source
AI summary
A method of tracing instruction execution on a processor of an integrated circuit chip in real time whilst the processor continues to execute instructions during clock cycles of the processor. The instruction execution of the processor is monitored by counting the number of successive instructions which are retired contiguously in time to form an instruction count, and counting the number of subsequent contiguous clock cycles of the processor during which no instruction is retired to form a stall count. A trace message is generated which includes the instruction count and the stall count, and the trace message is outputted.