Processor Utilization Simulation for Data Center Power Scheduling

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Solution Overview

Problem

Existing data center architectures face inefficiencies in processor utilization prediction and power management due to the complexity of CISC and RISC-based processors, leading to increased power consumption and costs.

Innovation Solution

A computer-implemented method using a machine learning processor utilization model trained with system log data and code feature data to predict and simulate processor utilization, enabling actions to optimize processor usage and reduce costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If CISC-based processors are used in data centers, then processing capability is improved, but power consumption increases

Engineering Contradiction:
Improveprocessing capabilityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent applies parameter changes by training machine learning models to predict processor utilization patterns and using this information to dynamically adjust system configuration, including selecting between CISC and RISC processor types based on predicted workload characteristics. This allows optimization of the processing capability to power consumption ratio by changing the operational parameters of the data center infrastructure.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements preliminary action by using machine learning models to predict future processor utilization patterns before workloads are executed. These predictions enable advance planning of resource allocation, processor selection, and scheduling decisions, allowing the system to prepare optimal configurations in advance rather than reacting to actual workload demands.

Inventive Principle:
Principle #10Preliminary action

2Power

If complex processor architectures are used, then processing power is improved, but system complexity increases

Engineering Contradiction:
Improveprocessing powerVSAvoidsystem complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The patent introduces machine learning models as intermediary components that mediate between the complex processor architectures and the workload management system. These models predict processor utilization patterns, enabling the system to make informed decisions about resource allocation and processor selection without directly managing the complexity of the underlying CISC or RISC architectures.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent creates simplified representations (copies) of complex processor utilization patterns through machine learning models. Instead of directly managing the complexity of CISC or RISC processor architectures, the system uses predicted utilization patterns as proxies to make scheduling and allocation decisions, effectively copying the essential behavioral characteristics without the full complexity.

Inventive Principle:
Principle #26Copying

3Measurement precision

If processor utilization prediction accuracy is improved, then resource allocation is optimized, but computational overhead increases

Engineering Contradiction:
Improveprediction accuracyVSAvoidcomputational overhead
Core Design Contradiction:
Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The patent applies partial action by training machine learning models on historical processor utilization data to capture key patterns without attempting to model every possible variable. The models focus on the most significant predictors of processor utilization, achieving sufficient accuracy for resource allocation decisions while avoiding the computational overhead of exhaustive analysis.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20250342102A1Machine learning model-based simulation of processor utilization
Publication Date: 2025.11.06 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US20250342102A1 patent drawing
  • US20250342102A1 patent drawing
  • US20250342102A1 patent drawing

AI summary

A machine learning-based processor utilization prediction process is provided which includes training a processor utilization model using system log data, code feature data, and processor-associated data of a system to, at least in part, predict processor utilization to execute application code on the system. In addition, the process includes generating, using the processor utilization model, a processor utilization simulation for the system to execute the application code, and initiating an action based on the processor utilization simulation for the system to execute the application code.