Processor Variable Instruction Atomicity for Interrupt Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In real-time embedded applications, the execution of complex instructions that require multiple cycles can degrade performance due to conventional interrupt recognition at instruction boundaries, leading to inefficiencies in handling interrupts during prolonged instruction execution.
Innovation Solution
A processor with multiple execution units that can execute complex instructions in multiple cycles, allowing for atomic execution of certain portions and enabling interruptions during non-overlapping portions, facilitating timely interrupt handling and parallel execution of different instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If complex instructions are executed for multiple cycles, then processing capability is improved, but interrupt response time deteriorates
Solution Approach 1:
The complex instruction execution is segmented into multiple cycles, with specific portions marked as atomic (non-interruptible) and others as interruptible. This segmentation allows the processor to maintain long execution sequences for complex instructions while permitting interrupts at safe boundaries, thus resolving the contradiction between processing capability and interrupt response time.
Solution Approach 2:
The patent introduces dynamic control over interrupt recognition during instruction execution. The interrupt recognition mechanism is made dynamic by allowing interrupts during non-atomic portions of multi-cycle instructions while blocking them during atomic portions. This dynamic approach enables the system to adapt interrupt responsiveness based on the criticality of the current execution phase.
2Reliability
If atomic execution is enforced during entire complex instruction, then execution integrity is improved, but interrupt handling efficiency deteriorates
Solution Approach 1:
Different portions of the complex instruction are assigned different atomicity properties. Critical portions are marked as atomic to ensure execution integrity, while non-critical portions are marked as interruptible to improve interrupt handling efficiency. This local differentiation of quality properties allows the system to maintain reliability where needed while optimizing productivity elsewhere.
Data Source
AI summary
A processor includes a plurality of execution units. At least one of the execution units is configured to execute a complex instruction that requires multiple instruction cycles to execute, and to enforce atomic execution of the complex instruction during a first-portion of the multiple instruction cycles required to execute the complex instruction. The at least one of the execution units is further configured to enable execution of the complex instruction to be interrupted for execution of a different instruction by the at least one execution unit during execution of a second portion of the multiple instruction cycles. The first portion and the second portion are non-overlapping.