Processor Verification CRC Calculation Merging
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Solution Overview
Problem
Current processor testing methods require significant time for result comparison during the validation and verification stage, which reduces the time available for test pattern execution and limits test coverage.
Innovation Solution
A system and method that share memory between multiple test patterns and perform memory error detection checks only after all test patterns have executed at least once, allowing for optimized result checking and increased processor design verification and validation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory error detection checks are performed after each test pattern execution, then error detection reliability is improved, but verification time increases
Solution Approach 1:
The patent merges multiple memory error detection checks into a single consolidated check performed after all test patterns have executed. Instead of performing separate CRC calculations after each individual test pattern, the system accumulates all test patterns in shared memory and performs one unified memory error detection check at the end, thereby maintaining reliability while significantly reducing verification time.
Solution Approach 2:
The patent performs preliminary actions by pre-loading all test patterns into shared memory before execution begins. The test patterns are prepared and stored in advance in the shared memory space, allowing the execution phase to proceed without interruption for intermediate checks, thus optimizing the timing structure to reduce overall verification time.
2Measurement precision
If more time is allocated for result comparison, then measurement precision is improved, but test pattern execution time decreases
Solution Approach 1:
The patent combines multiple intermediate result comparisons into a single final comparison. By merging the CRC calculation operations that would otherwise be performed after each test pattern into one consolidated memory error detection check, the system maintains precise measurement of test results while freeing up execution time for running more test patterns.
Solution Approach 2:
The patent ensures continuous test pattern execution by eliminating interruptions for intermediate verification. The shared memory structure allows test patterns to be executed back-to-back without pausing for CRC calculations, maintaining continuous useful action during the execution phase while still performing precise result comparison in the final verification stage.
3Adaptability or versatility
If separate memory is allocated for each test pattern, then test pattern independence is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal shared memory structure that serves multiple test patterns simultaneously. This single memory space is designed to accommodate and manage multiple test patterns through standardized addressing and control mechanisms, providing test pattern independence through logical separation rather than physical isolation, thereby reducing device complexity while maintaining versatility.
Solution Approach 2:
The patent segments the shared memory into distinct logical regions or address spaces that correspond to different test patterns. This logical segmentation allows each test pattern to be independently managed and verified while physically sharing the same memory hardware, thus reducing device complexity compared to having completely separate physical memory for each pattern.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces verification time by minimizing the time spent on memory error detection checks, thereby increasing the time available for test pattern execution and enhancing overall test coverage.
Implementation Method 1
For example, the simulation register/memory error detection check values may be computed using a cyclic redundancy check (CRC).
Data Source
AI summary
A system and method to reduce verification time by sharing memory between multiple test patterns and performing results checking after each test pattern executes one time is presented. A test pattern generator generates multiple test pattern sets, each of which including multiple test patterns. Each test pattern set is executed by a corresponding thread/processor until each test pattern included in the test pattern set has executed at least once. After all test patterns have executed at least once, a test pattern executor performs a memory error detection check to determine whether the system is functioning correctly. Since the invention described herein waits until all test patterns have executed before performing a memory error detection check, less time is spent on memory error detection checks, which allows more time to execute test patterns.