Processor Vertex Debugging via Thread-Scoped Breakpoints
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Solution Overview
Problem
Debugging multi-tile, multi-threaded processor architectures executing machine intelligence algorithms is challenging due to the complexity of managing and inspecting vertices in a graph-based computation environment, where parallelism and concurrency lead to difficulties in identifying and addressing errors within the processor.
Innovation Solution
The processor architecture allocates each vertex to a thread and uses debug hardware to raise an instruction exception only when a vertex break identifier matches the vertex being processed, enabling targeted debugging while allowing other threads to continue executing, and employs a bulk synchronous parallel scheme to synchronize threads across tiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional debugging methods are used in multi-tile, multi-threaded processors, then all threads must be stopped for inspection, but this causes loss of processing time and reduces productivity
Solution Approach 1:
The processor divides debugging capability into separate debug units, one for each thread, allowing independent inspection of individual threads without affecting others. Each debug unit can capture and hold thread state independently, enabling precise debugging of specific threads while maintaining execution of others.
Solution Approach 2:
Instead of stopping all threads for debugging, the system applies debugging action only to the specific thread that requires inspection. The debug unit selectively captures state from individual threads based on debug requests, performing partial debugging action that minimizes impact on overall processing productivity.
2Speed
If multiple execution pipelines are provided for parallelism, then processing speed is improved, but hardware complexity and silicon area increase significantly
Solution Approach 1:
Multiple threads share a common execution pipeline rather than each thread having a dedicated pipeline. The pipeline is time-multiplexed across threads, merging resources to reduce hardware complexity and silicon area while maintaining parallel processing capability through concurrent thread execution.
Solution Approach 2:
The execution pipeline switches between different threads in periodic time slots, allowing each thread to execute instructions during its allocated period. This periodic time-multiplexing enables parallelism effects without requiring simultaneous dedicated pipelines for each thread, reducing hardware complexity.
3Device complexity
If threads share a common execution pipeline, then hardware complexity is reduced, but pipeline latency must be hidden through increased interleaving
Solution Approach 1:
The processor dynamically schedules threads across the execution pipeline, adjusting which thread executes at each time slot based on thread state, priority, and pipeline availability. This dynamic interleaving maximizes pipeline utilization and hides latency by continuously switching between threads to keep the pipeline full.
Solution Approach 2:
The system monitors pipeline status and thread execution progress, using this feedback to adjust scheduling decisions. When pipeline latency is detected or threads stall, the scheduler increases interleaving of other threads to maintain processing efficiency and keep the pipeline actively utilized.
Data Source
AI summary
A method for debugging a processor which is executing vertices of a software application is described. Each vertex is assigned to a programming thread of the processor. The processor has debug hardware for raising exceptions in certain break conditions. The method comprises inspecting a vertex identifier, comparing the vertex identifier and raising an instruction exception event for the programming thread if the vertex identifier assigned to the thread matches the vertex break identifier in the debug hardware. Exceptions are raised based on identified vertices, rather than just individual instructions or instruction addresses.