Processor Virtual Ports for Pin Configuration and Data Transfer
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Solution Overview
Problem
Current MCU GPIO and IOMUX designs with discrete ports/pins require excessive configuration effort, degrade performance for data transfer, and make test software non-reusable due to varying port bus widths.
Innovation Solution
A processor with programmable virtual ports that group selected IO pins from multiple predefined ports, allowing simultaneous access and reducing the need for bit-mode programming, thereby enhancing application performance and test efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If discrete ports/pins are used in current MCU GPIO and IOMUX design, then the processor can support different system requirements and pin configurations, but it requires extra configuration effort and degrades data transfer performance
Solution Approach 1:
The patent implements a unified port interface that can function as multiple discrete ports through configuration. A single physical port structure serves universal purposes by being programmable to behave as different port widths (8-bit, 16-bit, 32-bit) and support various pin multiplexing configurations, eliminating the need for separate physical port structures for each configuration scenario.
Solution Approach 2:
The port interface is designed to be dynamically reconfigurable through software programming. The port width, pin assignments, and functional configurations can be changed at runtime without hardware changes, allowing the same physical structure to adapt to different system requirements dynamically rather than being fixed at manufacturing.
2Adaptability or versatility
If discrete ports/pins are used, then the processor can accommodate varying pin multiplexing configurations, but data transfer performance is degraded and execution time increases
Solution Approach 1:
The patent merges multiple discrete port interfaces into a single unified port structure. By combining the functionality of multiple separate ports into one integrated interface, the system achieves faster data transfer through a single optimized pathway rather than multiple slower discrete pathways, while maintaining the ability to configure the unified port to emulate different discrete port arrangements.
3Adaptability or versatility
If discrete ports with varying bus widths are used, then the processor can support different package configurations, but test software becomes non-reusable and verification time increases
Solution Approach 1:
The unified port interface provides a universal testable structure that can be programmed to represent different package configurations and bus widths. Test software can target this single universal interface and automatically adapt to different configurations through programming rather than requiring separate test software for each package type, making test software reusable across different product variants.
4Adaptability or versatility
If multiple discrete ports are used, then the processor can provide comprehensive IO functionality, but the port program becomes complex and harder to configure
Solution Approach 1:
The unified port interface is segmented into programmable sub-units that can be independently configured. Each physical pin or group of pins can be assigned to different functional segments through software, allowing comprehensive IO functionality to be achieved through logical segmentation rather than physical complexity. This segmentation is managed through a single configuration interface rather than multiple separate port programs.
Data Source
AI summary
A processor with programmable virtual ports includes a plurality of in/out (IO) pins for transmitting and receiving data. The IO pins are grouped into a plurality of predefined ports, each of which has a physical address stored in one of a memory location of a memory map. The IO pins may be remapped to one or more virtual ports.