Adaptable Voltage Margin for Processor Clock Stability
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Solution Overview
Problem
Variations in processor operating conditions, such as voltage noise, cause timing errors and fluctuations in clock frequency, which can adversely affect processor operations in applications like gaming and server systems, and increasing supply voltage to mitigate this increases power consumption.
Innovation Solution
An adaptive clock module adjusts the voltage margin of the supply voltage based on sampled clock frequency variations, using a digital frequency-locked loop and voltage margin control module to maintain a stable clock frequency within specified limits, reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the supply voltage is increased above a threshold amount to reduce clock frequency variations, then the stability of clock frequency is improved, but the power consumption increases
Solution Approach 1:
The patent implements dynamic voltage margin adjustment where the voltage margin is continuously adapted based on real-time clock frequency measurements. The adaptive clock module monitors clock frequency and dynamically modifies the voltage margin to maintain frequency stability only when necessary, rather than maintaining a constantly high voltage margin, thereby reducing overall power consumption while preserving clock frequency stability during critical operations.
Solution Approach 2:
The system changes the voltage margin parameter dynamically based on operating conditions. By adjusting the voltage margin parameter in response to measured clock frequency variations, the system optimizes the balance between clock frequency stability and power consumption, applying voltage increases only when frequency drift exceeds acceptable thresholds.
2Reliability
If an adaptive clock module is used to adjust clock frequency based on voltage variations, then timing errors are reduced, but the device complexity increases
Solution Approach 1:
The adaptive clock module incorporates a feedback mechanism that measures the actual clock frequency and uses this information to adjust the voltage margin. The clock frequency measurement unit continuously monitors frequency deviations and feeds this information back to the voltage margin control, creating a closed-loop system that automatically corrects timing errors without requiring complex external control circuits.
Solution Approach 2:
The adaptive clock module is designed to self-regulate by automatically adjusting its own operating parameters. The module monitors its own clock frequency output and autonomously modifies the voltage margin to maintain timing accuracy, eliminating the need for external control systems and reducing overall device complexity while maintaining high timing reliability.
Data Source
AI summary
A processor adjusts the voltage margin of a supply voltage based on a sampled clock frequency. The processor generates the supply voltage by combining the voltage margin with a specified nominal voltage, and provides the supply voltage to a processor module, such as graphics processing unit (GPU). In addition, an adaptive clock module (e.g., a digital frequency-locked loop) generates a clock signal for the processor module, wherein the frequency of the clock signal varies at least in part based on the supply voltage. The processor samples the frequency of the clock signal and adjusts the voltage margin based on the sampled frequency. The processor thereby keeps excursions in the clock frequency within a specified limit, thus supporting a relatively stable clock frequency.