Processor Voltage Ramp Preemption for Exit Latency
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Solution Overview
Problem
Modern computing devices face challenges in energy efficiency due to increased power requirements, particularly in small form factor devices where processors need to maintain performance while minimizing exit latencies from idle states, which puts additional burden on power delivery components.
Innovation Solution
The implementation of a processor configuration that allows for independent voltage and frequency control of each core through integrated voltage regulators, with a power control unit managing voltage ramps and prioritizing low power state exits to reduce latency and improve responsiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If voltage is increased quickly to exit idle state, then processor performance is improved, but power delivery component burden increases
Solution Approach 1:
The processor predicts future voltage requirements based on scheduled events (interrupts, performance state changes, power state exits) and begins voltage ramps in advance. This preliminary action allows the voltage to be ready before it is actually needed, reducing exit latency without requiring excessive peak current from power delivery components.
Solution Approach 2:
The voltage ramp rate is dynamically adjusted based on the predicted timeline of events. The system optimizes the ramp rate to achieve the required voltage level exactly when needed, rather than using a fixed fast ramp rate that would overburden power delivery components. This dynamic adjustment balances performance requirements with power delivery capabilities.
2Productivity
If multiple voltage ramps are scheduled, then processor responsiveness is improved, but voltage ramp conflicts increase
Solution Approach 1:
The system implements a feedback mechanism where the completion status of voltage ramps is tracked and used to adjust future ramp scheduling. When a voltage ramp is predicted to conflict with an event requirement, the system adjusts the ramp schedule based on feedback about actual voltage levels and event timing, resolving conflicts while maintaining responsiveness.
3Loss of time
If voltage ramp rate is increased, then exit latency is reduced, but power delivery component capability requirements increase
Solution Approach 1:
By predicting when voltage will be needed and starting voltage ramps early, the system can use moderate ramp rates that don't overburden power delivery components. The voltage is increased in advance rather than requiring high peak power delivery when the exit actually occurs.
Solution Approach 2:
The voltage ramp rate is dynamically optimized based on the time available before voltage is needed. When there is plenty of time, slower ramp rates are used to reduce power delivery burden. When time is critical, faster ramp rates are used, but only when necessary and within component capabilities.
Data Source
AI summary
In one embodiment, a processor includes a plurality of cores and a power controller. This power controller in turn may include a voltage ramp logic to pre-empt a voltage ramp of a voltage regulator from a first voltage to a second voltage, responsive to a request for a second core to exit a low power state. Other embodiments are described and claimed.