Pipelined Processor Wake-Up Initialization
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Solution Overview
Problem
Current processor initialization methods, such as using a state machine to load microcode, result in delays and require additional hardware, as they need to load instructions into the pipeline after a wake-up event, which can lead to undesired operations and increased timing cycles.
Innovation Solution
Incorporating settable elements in the pipeline stages to preload instructions or decoded instructions in response to a wake-up event, allowing for immediate execution and reducing the need for a conventional hardware boot-up sequence by preloading instructions that can perform initialization routines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a state machine is used to load microcode into the pipeline, then the processor can achieve the desired initialisation effects, but this adds hardware complexity and increases the time required for the processor to be ready
Solution Approach 1:
The patent pre-loads initialisation instructions into the pipeline stages before normal operation begins. The storage elements in pipeline stages are configured to hold specific instruction values that are automatically executed when the processor wakes from reset, eliminating the need for a runtime state machine to load microcode.
Solution Approach 2:
The patent extracts the initialisation functionality from a separate state machine component and integrates it directly into the pipeline storage elements. By embedding the initialisation instructions within the pipeline stages themselves, the complex state machine hardware is eliminated while retaining the necessary initialisation capability.
2Productivity
If instructions are loaded into the pipeline after a wake-up event, then the processor can execute initialisation routines, but this adds timing delays to processor readiness
Solution Approach 1:
The patent prepares initialisation instructions in advance by storing them in the pipeline stage storage elements before the wake-up event. When the processor wakes, these instructions are already positioned in the pipeline and can be executed immediately without waiting for loading, thus reducing the time loss before the processor becomes fully operational.
3Reliability
If values are stored at start-up in instruction registers within the pipeline, then the pipeline can be initialised, but this creates the additional task of ensuring they do not generate undesired operations
Solution Approach 1:
The patent introduces a control mechanism that mediates between the pre-stored initialisation values in the pipeline and the execution unit. This control logic ensures that the initialisation values are executed at the appropriate time (immediately after wake-up) and then disabled or masked to prevent them from generating undesired operations during normal operation.
Data Source
AI summary
A data processing apparatus is disclosed that comprises a pipelined processor, said pipelined processor comprising a processing pipeline for processing instructions in a plurality of stages, at least some of said plurality of stages each comprising storage elements for storing an instruction or decoded instruction being processed in said stage, said storage elements in at least one of said stages comprising settable elements, each of said settable elements being adapted to store a predetermined value in response to a wake up event, said settable elements being arranged such that in response to said wake up event said values stored in said settable elements form an instruction or decoded instruction.