Processor Wrapper for 2.5D DRAM Test Area Overhead
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Solution Overview
Problem
Conventional test architectures for 2.5D/3D system chips face challenges in efficiently testing stacked dynamic random access memory (DRAM) dies and interconnects, particularly in minimizing area overhead and ensuring compliance with industry standards like IEEE 1149.1 for board-level integration.
Innovation Solution
A test architecture that includes an interposer-mounted logic die with a processor wrapper and a memory die, featuring channel selection/bypass logic controlled by the processor wrapper, enabling individual die testing and interconnect testing while reusing System on a Chip (SoC) test infrastructure and adhering to IEEE standards, such as IEEE 1149.1 and IEEE 1500.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional test architectures are used for 2.5D/3D system chips, then testing of stacked DRAM dies and interconnects can be performed, but area overhead increases and compliance with IEEE 1149.1 standards becomes difficult
Solution Approach 1:
The processor wrapper is designed to serve dual purposes: it functions as a standard processor interface during normal operation and simultaneously provides test access port (TAP) controller functionality for IEEE 1149.1 compliance testing. This multi-functionality eliminates the need for separate dedicated test control logic, thereby reducing area overhead while ensuring standard compliance
Solution Approach 2:
The test architecture merges the processor wrapper with the TAP controller and integrates boundary scan logic directly into the processor interface. This consolidation combines multiple test control functions into a unified structure, reducing the overall test infrastructure area while maintaining full IEEE 1149.1 compliance for testing stacked DRAM dies and interconnects
2Reliability
If individual die testing and interconnect testing are enabled, then testing completeness improves, but device complexity increases
Solution Approach 1:
The test architecture is segmented into modular components: the processor wrapper forms one module, the TAP controller forms another, and boundary scan logic is distributed across different interface points. This segmentation allows individual die testing and interconnect testing to be enabled through standardized modular interfaces without requiring a completely complex custom test architecture
Solution Approach 2:
The processor wrapper acts as an intermediary layer between the test equipment and the stacked DRAM dies/interconnects. It provides standardized TAP controller interfaces that mediate between external test equipment and the internal test logic, enabling comprehensive testing while maintaining architectural simplicity through standardization
Data Source
AI summary
A 2.5D or 3D test architecture includes a logic die, and a memory die. In the 2.5D architecture, the logic die and memory die are mounted on an interposer. In the 3D architecture, the memory die is mounted on the logic die. The logic die includes a control logic wrapped with a processor wrapper. The processor wrapper enables testing components of the control logic. The memory die is also mounted on the interposer. The memory die includes dynamic random access memory and channel selection/bypass logic. The control logic is coupled to the dynamic random access memory via the channel selection/bypass logic, the channel selection/bypass logic being controlled by the processor wrapper.