Processor xqFP Floating-Point Storage with Deferred-Increment Rounding

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Solution Overview

Problem

Existing floating-point formats like QFloat do not comply fully with the IEEE-754 standard, leading to issues such as lack of representation for positive zero, negative zero, infinity, and NaN values, and introduce errors due to implied LSBs, while fully compliant IEEE-754 implementations are resource-intensive.

Innovation Solution

An extended QFloat format (xqFP) is introduced, featuring an exponent field and a significand field formatted as a signed one's complement with an explicit MSB and a deferred increment bit representing ½ ULP, allowing for conversion to and from IEEE-754 compliant values while maintaining hardware efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If QFloat format is used for floating-point representation, then hardware efficiency is improved, but IEEE-754 compliance and precision are degraded

Engineering Contradiction:

Improvehardware efficiencyVSAvoidIEEE-754 compliance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The floating-point number is segmented into three distinct fields: sign bit, exponent field, and significand field. This segmentation allows the xqFP format to maintain hardware efficiency through structured representation while achieving IEEE-754 compliance through proper field organization and interpretation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the interpretation parameters of the floating-point format by using one's complement representation for the significand field and incorporating a deferred increment bit. These parameter changes enable the format to achieve IEEE-754 compliance while maintaining hardware efficiency through optimized rounding behavior and special value representation.

Inventive Principle:

Principle #35Parameter changes

2Ease of manufacture

If QFloat format is used, then hardware efficiency is improved, but precision and representation accuracy are degraded

Engineering Contradiction:

Improvehardware efficiencyVSAvoidfloating-point precision

Core Design Contradiction:

Ease of manufactureVSMeasurement precision

Solution Approach 1:

The deferred increment bit is set in advance to represent ½ ULP (Unit in the Last Place) before rounding operations are performed. This preliminary action eliminates the need for complex rounding logic during computation, maintaining hardware efficiency while achieving precise rounding results that match IEEE-754 requirements.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent replaces complex rounding mechanics with a simpler bitwise operation approach. By using one's complement representation and the pre-set deferred increment bit, the system substitutes complex rounding logic with more efficient bitwise operations, maintaining hardware efficiency while improving precision.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If full IEEE-754 compliance is implemented, then precision and special value representation are improved, but processor area and timing paths increase

Engineering Contradiction:

ImproveIEEE-754 complianceVSAvoidprocessor area

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The xqFP format implements a partial IEEE-754 compliance approach by adopting the essential structure (sign, exponent, significand fields) and rounding behavior, while simplifying certain aspects like the representation method. This partial implementation achieves sufficient compliance for most applications while avoiding the full complexity and area overhead of complete IEEE-754 implementation.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The patent uses a simplified floating-point representation that can be converted to and from IEEE-754 format when needed. This approach uses a more efficient internal representation (xqFP) for computations, reserving full IEEE-754 compliance only for interface operations, thereby reducing overall processor area while maintaining compatibility.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

4Ease of manufacture

If QFloat format with implied LSB is used, then hardware efficiency is improved, but rounding accuracy is degraded

Engineering Contradiction:

Improvehardware efficiencyVSAvoidrounding accuracy

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The deferred increment bit is pre-set to represent ½ ULP before rounding operations occur. This preliminary action eliminates the need for complex rounding logic during computation, maintaining hardware efficiency while achieving precise rounding results that match IEEE-754 requirements.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20250238199A1STORING FLOATING-POINT VALUES ACCORDING TO AN EXTENDED QFLOAT FLOATING-POINT (xqFP) FORMAT IN PROCESSOR DEVICES

Publication Date: 2025.07.24 QUALCOMM INC

AI summary

Storing floating-point values according to an extended QFloat floating-point (xqFP) format in processor devices is disclosed herein. In some aspects, a processor device comprises a register file comprising a plurality of registers, and comprises a floating-point unit (FPU) circuit that is configured to store a first floating-point value in a register of the plurality of registers. The first floating-point value is formatted according to the xqFP format that comprises an exponent field and a significand field. The significand field is formatted as a signed one's complement value, and comprises a sign bit, an explicit most-significant-bit (MSB), a fractional field, and a deferred increment bit that represents a value of one-half (½) unit of least precision (ULP).