Processor Y Logic Generates Reference Clock for ASIC Initialization
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Solution Overview
Problem
Conventional digital systems face challenges in synchronizing clock signals across all chips during initialization, making it difficult to ensure simultaneous initialization of all components.
Innovation Solution
The digital system employs a processor chip with elastic interface domains containing processor X and Y logics, which generate and distribute clock signals to ASIC chips, allowing for simultaneous functional mode operation and scanning mode functionality, ensuring all chips receive clock signals during initialization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional digital systems use standard clock distribution methods, then the system structure remains simple, but all chips cannot receive clock signals simultaneously during initialization
Solution Approach 1:
The processor is divided into two independent logic domains (X logic and Y logic) that can operate in different modes simultaneously. Each domain has its own clock control mechanism, allowing the Y logic to generate reference clock signals while the X logic performs scanning operations. This segmentation enables simultaneous initialization of multiple chips without requiring a completely redesigned clock distribution system.
Solution Approach 2:
The Y logic is configured to generate reference clock signals to ASIC chips before the X logic completes its scanning mode operations. This preliminary action ensures that clock signals are available to all chips during initialization, allowing them to start their boot processes simultaneously even though the X logic is still being tested through scanning.
2Reliability
If the processor X logic operates in scanning mode for testing, then testing coverage is improved, but clock signals cannot be provided to ASIC chips
Solution Approach 1:
By separating the processor into X logic (for scanning/testing) and Y logic (for clock generation), the system can maintain full testing coverage on the X logic while simultaneously providing clock signals through the Y logic. This allows scanning operations and clock distribution to occur in parallel without interfering with each other.
Solution Approach 2:
The Y logic acts as an intermediary that provides clock signals to ASIC chips independently of the X logic's scanning operations. This intermediary function ensures that even when the X logic is occupied with testing, the ASIC chips still receive the necessary clock signals for initialization and can proceed with their boot processes.
3Reliability
If the processor Y logic operates in scanning mode, then scanning functionality is achieved, but reference clock signals cannot be generated for ASIC chips
Solution Approach 1:
The processor is segmented into X logic and Y logic with distinct functional responsibilities. The Y logic is specifically designated for clock signal generation and remains in functional mode to continuously provide reference clock signals to ASIC chips, while the X logic handles scanning operations. This clear segmentation ensures both scanning functionality and clock signal generation are maintained simultaneously.
Data Source
AI summary
A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first processor X and Y logic comprise first X and Y latches, respectively; and a first ASIC chip electrically coupled to the processor chip, wherein the first processor X and Y logics are configured to be simultaneously in a functional mode, wherein the first processor X logic is configured to switch from the functional mode to a scanning mode while the first processor Y logic remains in the functional mode, and wherein in response to the first processor Y logic being in the functional mode, the first processor Y logic is configured to generate a first reference ASIC clock signal to the first ASIC chip.