Producer Consumer Remote Synchronization via Ordered Relaxed Writing
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Solution Overview
Problem
Software operating on multi-processor computing systems face challenges in ensuring ordered writing of data packets and associated semaphore packets, leading to reduced data transfer rates and increased latency when strict ordering or interrupt-based solutions are implemented.
Innovation Solution
A method involving ordered writing of data packets and a semaphore packet from a source device to a bridge interface device, followed by relaxed writing to target memory addresses, where the memory command processing unit monitors the semaphore and issues a synchronization command upon detection, resulting in a synchronization confirmation reply after all data packets are written.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strict ordered writing is configured to guarantee data and semaphore packet ordering, then data integrity is improved, but data transfer rate deteriorates
Solution Approach 1:
The patent segments the writing process into two distinct phases: ordered writing phase (where data packets and semaphore are written in strict order to ensure integrity) and relaxed writing phase (where writing order can be flexible to improve transfer rate). This segmentation allows the system to switch between strict and relaxed ordering based on current operational needs, resolving the contradiction between data integrity and transfer rate.
Solution Approach 2:
The patent implements dynamic switching between ordered and relaxed writing modes. The system can transition from strict ordering to relaxed ordering and back again based on operational context. This dynamic behavior allows the system to optimize for either data integrity or transfer rate depending on current requirements, eliminating the need to permanently choose one mode over the other.
2Reliability
If interrupt-based forcing of data visibility is implemented upon semaphore detection, then data synchronization is improved, but latency increases
Solution Approach 1:
The patent performs preliminary actions by writing data packets and semaphores in a predetermined ordered fashion during the ordered writing phase. This preliminary structured writing ensures that when relaxed writing begins, the foundation for proper synchronization is already established, reducing the need for interrupt-based forcing and thereby reducing latency.
Solution Approach 2:
The patent introduces an intermediary mechanism (the ordered writing phase acting as a buffer or preparation stage) between the producer and consumer. This intermediary structured writing phase ensures proper synchronization semantics are established before relaxed writing begins, eliminating the need for interrupt-based synchronization and reducing overall latency.
3Productivity
If relaxed writing is implemented to improve data transfer rate, then productivity is improved, but ordering guarantee deteriorates
Solution Approach 1:
The patent segments the writing operation into ordered writing (guaranteeing order) and relaxed writing (improving rate). By separating these two functions into distinct phases, the system can enjoy the benefits of both strict ordering and relaxed ordering without compromising either data integrity or transfer rate.
Solution Approach 2:
The patent maintains continuity of useful action by seamlessly transitioning between ordered and relaxed writing phases. The ordered writing phase prepares the data with proper ordering guarantees, and the relaxed writing phase continues the data transfer at higher rates. This continuous operation ensures both ordering guarantees and high transfer rates are achieved without interruption.
Data Source
AI summary
Remotely synchronizing data communicated in an electronic computing system. Ordered writing of a data set of discrete data packets (data) and a following associated semaphore packet (semaphore) from a source electronic device (source) to a bridge interface device (bridge). Relaxed writing of the data set from the bridge to discrete target memory addresses (targets) of a data-consuming electronic device (consumer), wherein the order of the data and the semaphore written to the targets is different than the order of the data and semaphore written with the ordered writing. Monitoring, by the consumer, the relaxed writing of the semaphore to one of the targets. Issuing a synchronization command to the bridge upon detection of the semaphore having been written to the one target. Sending a synchronization confirmation reply from the bridge after all of the data has been written to the targets.