Symmetry-Invariant Product Code Decoder With Single-Dimension Access
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Solution Overview
Problem
Conventional hardware implementations of half product code (HPC) decoding require expensive circuitry to access data in both row and column formats, leading to high latency and inefficiency, especially in high-performance applications.
Innovation Solution
A hardware decoder that accesses binary symmetry-invariant product codes along only one dimension, utilizing error correction circuits to detect and correct errors based on data symmetry, reducing the need for dual-dimensional access and lowering latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional hardware implementations access data in both row and column formats for HPC decoding, then error correction capability is improved, but implementation cost and latency increase
Solution Approach 1:
The patent applies asymmetry by breaking the symmetric dual-dimensional access structure of conventional HPC decoders. Instead of accessing data in both row and column formats, the invention accesses data along only one dimension (either row or column) while using error storage arrays to track and correct errors in the orthogonal dimension. This asymmetric approach reduces hardware complexity and latency while maintaining error correction capability through the use of symmetry properties of HPCs.
2Measurement precision
If conventional hardware implementations use dual-dimensional access for symmetry-invariant product codes, then decoding accuracy is improved, but device complexity increases
Solution Approach 1:
The patent extracts the column access functionality from the conventional dual-dimensional decoder architecture. Instead of implementing full row and column access circuitry, the invention extracts only the necessary error detection and correction logic for one dimension, while using error storage arrays to handle the orthogonal dimension. This extraction reduces device complexity by removing redundant access circuitry while preserving decoding accuracy through intelligent error tracking and correction.
3Reliability
If iterative decoding is performed by decoding C1 and C2 codewords sequentially, then error correction is achieved, but decoding time increases
Solution Approach 1:
The patent applies preliminary action by pre-processing and identifying errors in one dimension before fully decoding the other dimension. The error storage arrays are populated with error locations detected in the first dimension, which are then used to correct errors in the second dimension during the decoding process. This preliminary error identification accelerates the iterative decoding process by reducing the number of correction iterations needed, thereby improving decoding speed while maintaining error correction reliability.
Data Source
AI summary
A decoder for decoding a binary symmetry-invariant product code includes a data array having orthogonal first and second dimensions. The data array is configured to access a binary symmetry-invariant product code buffered therein along only the first dimension. The decoder also includes an error storage array for storing error locations and a first correction circuit configured to detect and correct errors in data accessed from the data array along the first dimension and to store error locations along the second dimension in the error storage array. The first correction circuit determines the error locations based on data symmetry of the symmetry-invariant product code. The decoder also includes a second correction circuit that, prior to receipt by the first correction circuit of data accessed from the data array along the first dimension, corrects the data accessed from the data array based on the error locations stored in the error storage array.