Profile Guided Buffer Sizing for FPGA High-Level Synthesis
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Solution Overview
Problem
In designing systems for target devices like FPGAs and ASICs, existing high-level synthesis methods lack integration with profile data, leading to inefficient buffer sizing, resulting in resource wastage or performance issues due to non-deterministic latencies.
Innovation Solution
Incorporating profile data collection hardware to monitor arrival and service rates, allowing for the construction of probability distributions to optimize buffer sizing based on percentile requirements during high-level and HDL compilation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional high-level synthesis is performed independent of profile data, then the compilation process is simpler and faster, but buffer sizing accuracy deteriorates leading to resource wastage or performance issues
Solution Approach 1:
The patent applies preliminary action by performing a first compilation to generate initial HDL code and collecting profile data from actual system operation before performing the second optimization compilation. This preliminary data collection enables accurate buffer sizing in the subsequent compilation without requiring complex real-time analysis during the optimization process.
Solution Approach 2:
The patent implements feedback by using profile data collected from the first compilation and system operation to guide the buffer sizing decisions in the second compilation. The profile data provides empirical feedback about actual system behavior, allowing the HDL compiler to optimize buffer sizes based on real-world performance characteristics rather than theoretical estimates.
2Measurement precision
If profile data collection hardware is added to monitor arrival and service rates, then buffer sizing accuracy improves, but device resource usage increases
Solution Approach 1:
The patent applies self-service by having the system monitor and collect its own operational profile data during normal operation. The profile data collection hardware works autonomously to gather arrival rates and service rates without requiring external measurement equipment, and this data is then reused in the compilation process to optimize the same system that generated the data.
Solution Approach 2:
The patent uses preliminary action by collecting profile data during a first compilation and system operation phase before the optimization compilation. This preliminary data collection captures real system behavior, and the same data is then utilized in the second compilation to determine optimal buffer sizes, avoiding the need for additional hardware during the optimization phase.
3Productivity
If buffer sizes are estimated without profile data, then the design process is faster, but system performance deteriorates due to non-deterministic latencies
Solution Approach 1:
The patent implements feedback by using empirically collected profile data from system operation to guide buffer sizing decisions. This feedback loop ensures that buffer sizes are determined based on actual system behavior and performance characteristics, improving reliability while the automated nature of the process maintains design productivity.
Solution Approach 2:
The patent applies preliminary action by collecting profile data and determining optimal buffer sizes during a first compilation phase before final system implementation. This preliminary optimization ensures that the system is configured with accurate buffer sizes from the start, improving performance without requiring iterative adjustments that would slow down the overall design process.
Data Source
AI summary
A method for designing a system on a target device includes generating a hardware description language (HDL) representation of profile data collecting hardware for a HDL of the system during a high-level compilation to collect profile data that includes an arrival rate associated with data transmitted to a buffer and a service rate of a service node associated with the buffer. The HDL of the system is compiled to generate a data file that describes a synthesis, placement and routing of the system on the target device. The target device is programmed with the data file to physically transform components on the target device to implement the system.