Profile Queue Wear Leveling Memory Devices
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Solution Overview
Problem
Existing memory devices face uneven wear across memory cells due to disproportionate read and write operations, leading to premature failure, and current wear leveling methods are resource-intensive.
Innovation Solution
A profile and queue-based wear leveling system that uses a logical-to-physical table, next address queues, and disposal address queues to distribute physical addresses based on usage profiles, ensuring even wear across memory cells with minimal resource overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If traditional wear leveling methods are used to distribute write operations evenly across memory cells, then the lifespan of memory devices is extended, but resource consumption increases
Solution Approach 1:
The patent segments memory addresses into multiple address spaces (first address space, second address space, third address space) with different wear characteristics. By dividing the address space and assigning different write allocation strategies to each segment, the system achieves wear leveling while reducing the computational overhead of tracking and managing individual cell wear states.
Solution Approach 2:
The patent changes the parameter of address space organization by creating multiple address spaces with different wear levels. This parameter change allows the system to distribute writes across spaces with varying durability characteristics, achieving effective wear leveling without requiring complex per-cell tracking mechanisms that would increase resource consumption.
2Use of energy by moving object
If write operations are concentrated on specific memory cells, then resource usage is reduced, but uneven wear leads to premature failure
Solution Approach 1:
By segmenting the address space into multiple spaces with different wear characteristics, the system can concentrate writes on more durable address spaces while protecting vulnerable ones. This segmentation allows resource-efficient write allocation without concentrating all writes on single cells, thereby preventing premature failure through diversified wear distribution.
Solution Approach 2:
The patent applies local quality by assigning different wear characteristics to different address spaces. Each address space can be optimized with appropriate write allocation policies based on its specific wear profile, allowing the system to balance resource efficiency with reliability by treating different regions differently rather than applying a uniform approach.
Data Source
AI summary
A method is described that includes receiving a write request with user data and a logical address and select a next address queue from a plurality of next address queues based on a reciprocal relationship between short-term usage information associated with the logical address and a set of characteristics of the selected next address queue. Each next address queue in the plurality of next address queues stores physical addresses that are designated to be used for fulfilling write requests. Further, a next physical address is removed from the selected next address queue and the user data of the write request is written to the next physical address in a memory device.