Profiled Interconnect Lines for Lower Capacitance at Tight Pitches
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges in reducing the capacitance of upper metal lines, which affect device performance, particularly in regions with tight pitches.
Innovation Solution
The formation of metal lines with specific width profiles, including a narrower middle section and varying dielectric layers with different etch selectivities, along with conformal liners, to create horizontal distance variations that reduce capacitance while maintaining acceptable resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the width of upper metal lines is reduced to decrease capacitance, then the capacitance is reduced, but the resistance increases
Solution Approach 1:
The metal line is designed with non-uniform width, featuring a narrower middle section and wider top and bottom sections. This local variation in geometry allows the line to have reduced capacitance in the middle section while maintaining lower resistance through the wider sections at the ends, thereby resolving the contradiction between reducing capacitance and controlling resistance
Solution Approach 2:
The metal line is effectively segmented into three sections with different widths: a top section, a narrower middle section, and a bottom section. This segmentation allows different portions of the same metal line to serve different functions - the wider sections minimize resistance while the narrower middle section reduces capacitance, thus resolving the contradiction
2Area of stationary object
If the pitch between metal lines is reduced to increase density, then the area is reduced, but the capacitance between adjacent lines increases
Solution Approach 1:
By making the middle section of metal lines narrower while keeping top and bottom sections wider, the invention creates local quality variations that reduce the effective overlapping area between adjacent lines in the critical middle region, thereby reducing inter-line capacitance even when lines are closely spaced
Solution Approach 2:
The metal line geometry is made asymmetric with respect to uniform width, creating a profile that is narrower in the middle and wider at the ends. This asymmetric design reduces the capacitive coupling between adjacent parallel lines by minimizing the overlapping surface area in the middle section where coupling is strongest
Data Source
AI summary
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a metal level that includes a metal line, the metal line includes a bottom section having a first width, a middle section having a second width, and a top section having a third width, where the second width of the middle section is narrower than the first width of the bottom section and is narrower than the third width of the top section. A method of forming the semiconductor structure is also provided.