Profiled Display Panel Cascade Traces With Dual-Layer Conductors
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Solution Overview
Problem
The high resistance of cascade signal lines between different Gate Drive In Active Area (GIA) groups in profiled display panels leads to cascading abnormalities, which affects the performance and functionality of the display.
Innovation Solution
The profiled display panel employs a dual-layer conductive structure for cascade traces, using a first conductive layer made of a source-drain metal layer with lower resistance and a second conductive layer made of a gate metal layer, along with via holes for electrical connections, to reduce resistance and prevent signal attenuation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-layer gate metal layer (GT layer) is used for cascade signal lines, then the device complexity is reduced, but the resistance is too high causing cascading abnormality
Solution Approach 1:
The patent uses a composite conductive structure combining a first conductive layer (source-drain metal layer) and a second conductive layer (gate metal layer) to form cascade signal lines. This composite structure reduces overall resistance by utilizing the low-resistance source-drain metal layer while maintaining the necessary conductive pathways, thereby solving the cascading abnormality issue without excessive complexity increase.
Solution Approach 2:
The patent transitions from a single-layer to a multi-layer conductive structure by adding vertical stacking dimensions. The first conductive patterns on the first conductive layer are electrically connected to the second conductive pattern on the second conductive layer through via holes, creating a three-dimensional conductive pathway that reduces resistance while managing complexity through structured layering.
2Ease of manufacture
If the cascade signal lines are made of Mo metal GT layer, then the manufacturing process is simplified, but the resistance is too high leading to signal attenuation
Solution Approach 1:
The patent combines Mo metal (gate metal layer) with source-drain metal layer materials to create a composite conductive structure. This allows the benefits of Mo metal's ease of manufacture to be retained while the low-resistance properties of the source-drain metal layer compensate for signal attenuation, achieving both manufacturability and signal quality.
3Reliability
If a dual-layer conductive structure with via holes is used, then the resistance is reduced and cascading abnormality is prevented, but the device complexity increases
Solution Approach 1:
The patent segments the conductive structure into distinct first and second conductive layers, each serving specific functions. The first conductive layer handles primary signal transmission with low resistance, while the second conductive layer provides additional conductive pathways. This segmentation allows for optimized performance while managing complexity through modular design.
Solution Approach 2:
The patent utilizes vertical stacking of conductive layers connected by via holes to reduce resistance without increasing lateral complexity. By moving to a three-dimensional conductive architecture, the patent achieves lower resistance paths while maintaining a compact planar footprint, effectively managing overall device complexity.
Data Source
AI summary
A profiled display panel, including a display area. The display area includes a plurality of display sub-areas; a plurality of cascade signal lines for coupling adjacent two of the gate driving sub-circuits. At least one cascade signal line includes a first cascade trace extending in a first direction and a second cascade trace extending in a second direction. The first cascade trace includes a plurality of first conductive patterns arranged on a first conductive layer and second conductive pattern arranged on a second conductive layer. The plurality of first conductive patterns are electrically connected to the second conductive pattern; and the second cascade trace includes a third conductive pattern arranged on the first conductive layer.