Program Conversion for Vector Processors via Loop Segmentation
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Solution Overview
Problem
Existing compilers fail to convert programs to highly efficiently executable object programs when they refer to memory areas with different variables from loop variables, leading to inefficient execution on vector processors due to discontinuous memory access.
Innovation Solution
A program conversion device that includes loop dividing, variables reallocating, and processing exchanging mechanisms to convert programs with termination determination processing, ensuring continuous memory access for vector processors by reallocating memory areas and rearranging processing orders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If existing compilers convert programs to object programs with vectorized loop processing, then execution speed on vector processors is improved, but memory access becomes discontinuous when reference variables are used, reducing execution efficiency
Solution Approach 1:
The patent segments the loop processing into two separate loops: the first loop processes continuous memory areas using loop variables, while the second loop processes discontinuous memory areas using reference variables. This segmentation allows each loop to be optimized independently for its specific memory access pattern, resolving the contradiction between vectorization benefits and memory access continuity requirements.
Solution Approach 2:
The patent introduces a new dimension of loop structure by creating nested loops with different purposes. The outer loop (first loop) handles the primary iteration with continuous memory access, while the inner loop (second loop) handles reference variable updates with discontinuous access. This dimensional change in program structure enables both vectorization and efficient memory access.
2Productivity
If compilers generate vectorized loop processing, then processing capability is enhanced, but the program cannot handle termination determination processing efficiently
Solution Approach 1:
The patent separates termination determination processing from the main vectorized loop by placing it in a distinct second loop that executes after each iteration of the first loop. This segmentation allows the vectorized processing to maintain high productivity while the separate termination check provides the necessary adaptability for conditional execution.
Solution Approach 2:
The patent uses the loop structure itself as an intermediary mechanism between the vectorized processing and termination determination. The first loop serves as the intermediary that performs bulk vectorized operations, while the second loop acts as the intermediary for termination checks, allowing both functions to coexist without interfering with each other's efficiency.
3Adaptability or versatility
If compilers convert programs including termination determination processing, then program functionality is preserved, but execution efficiency on vector processors deteriorates due to discontinuous memory access
Solution Approach 1:
By segmenting the processing into two loops with distinct memory access patterns, the patent preserves the full functionality of the original program (including termination determination) while minimizing the time loss associated with discontinuous memory access. The first loop handles the time-critical continuous access operations, while the second loop handles the less time-sensitive reference variable updates.
Solution Approach 2:
The patent applies local quality optimization by making the memory access pattern in the first loop continuous and optimized for vector processing, while allowing the second loop to handle the inherently discontinuous reference variable access. This localized optimization ensures that the most time-critical operations benefit from efficient memory access while preserving overall program functionality.
Data Source
AI summary
A program conversion device includes converting a program including second loop processing that repeats first processing and determination processing a plurality of times to a program including third loop processing and fourth loop processing; converting the converted program to a first-number-of-times repeating processing that includes second-number-of-times repeating processing of the first loop processing and the second-number-of-times repeating processing of the determination processing; converting the first processing and the determination processing to processing that accesses to memory areas that are different for fourth loop processing and that are continuous in a processing order in the fourth loop processing; and exchanging a processing order of the fourth loop processing and the first loop processing, wherein the third loop processing is the-first-number-of-times repeating processing related to the second loop processing, and the fourth loop processing is the-second-number-of-times repeating processing related to the second loop processing in the third loop processing.