Program Counter Tracing Circuit for Complete External Branch Trace
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Solution Overview
Problem
Conventional tracing methods require a tracing storage means within the LSI or outputting all address buses externally, and fail to accurately determine branch destination addresses due to incomplete information output.
Innovation Solution
A tracing circuit integrated with a microprocessor that synchronously outputs a tracing clock and data, allowing for external tracing by setting different values based on program counter states, and includes a status generator, counter, and selector to manage branch destination addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If a tracing storage means is provided inside the LSI, then complete tracing information can be obtained, but device complexity and overhead increase
Solution Approach 1:
The patent extracts the tracing storage function from the LSI internal architecture and relocates it to external memory. The tracing circuit outputs trace data to an external tracer, which stores the complete program counter history in external memory. This eliminates the need for internal tracing storage while maintaining complete tracing capability.
Solution Approach 2:
The patent introduces an external tracer as an intermediary component between the LSI and the tracing storage. The tracer receives trace data from the LSI's tracing circuit, reconstructs the complete program counter history, and stores it in external memory. This intermediary handles the storage function externally, reducing LSI complexity.
2Loss of information
If all address buses are output to outside the LSI, then complete address tracing is enabled, but device complexity and pin requirements increase
Solution Approach 1:
The patent extracts only the necessary program counter information from the LSI and outputs it to external memory through a simplified tracing circuit. Instead of outputting all address buses, the system extracts and outputs only the program counter values, reducing the amount of data transmitted while maintaining complete tracing capability.
Solution Approach 2:
The patent segments the address bus output into discrete program counter values. Rather than continuously outputting all address bus signals, the tracing circuit captures and outputs only the program counter values at relevant events (instruction fetches, branches, interrupts), segmenting the continuous address stream into discrete, meaningful trace entries.
3Device complexity
If only part of branch information is output, then device complexity is reduced, but tracing precision is lost
Solution Approach 1:
The patent extracts complete program counter values including full branch destination addresses from the LSI and outputs them to external memory. The tracing circuit captures the entire program counter state at branch points, ensuring that complete branch destination address information is available externally without requiring complex internal tracing storage.
Solution Approach 2:
The patent performs preliminary capture of the complete program counter value before the branch execution completes. By capturing the program counter state at the appropriate timing (when the branch destination address is available in the program counter register), the system ensures complete branch information is recorded before the actual branch execution occurs.
Data Source
AI summary
A tracing circuit is integrated in a semiconductor device along with a microprocessor including an m-bit program counter, and externally outputs a tracing clock along with an n-bit tracing data (where 2≤n≤m). The tracing circuit, when the program counter remains unchanged, synchronously with the tracing clock sets the tracing data to a first output value; when the program counter is incremented, synchronously with the tracing clock sets the tracing data to a second output value; and when the program counter is loaded, synchronously with the tracing clock sets the tracing data to a third output value, and then suspends the state machine in the microprocessor and split-outputs, as the tracing data, the branch destination address or interrupt destination address loaded in the program counter.