Program Counter Compression Circuit with Differential Dictionary Encoding
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Solution Overview
Problem
Existing program counter compression methods are inefficient due to high hardware resource and power consumption, and they do not effectively combine architecture-based and lossless data compression techniques, particularly neglecting stall instructions which impact compression effectiveness.
Innovation Solution
A three-stage compression method involving instruction classification, differential slicing, and dictionary encoding, which classifies instructions, calculates and slices differential values, and uses a RAM-based LZ dictionary encoding to reduce resource and power consumption, specifically designed for the 'microcontroller+coprocessor' architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hardware module is embedded in processor to record path information in real time, then information collection speed is improved, but on-chip memory size and data transmission bandwidth are consumed
Solution Approach 1:
The patent extracts only the essential path information (program counter values at specific control flow points) rather than recording all instruction executions. By taking out only the critical jump, branch, and return instruction PC values, the system achieves fast real-time collection while minimizing memory consumption.
Solution Approach 2:
The patent applies different recording strategies to different instruction types based on their local characteristics. Control flow instructions (jump, branch, return) are recorded with full PC values, while sequential instructions are inferred or skipped. This local differentiation optimizes both collection speed and memory usage.
2Quantity of substance
If dictionary coding is applied to compress program counter, then compression ratio is improved, but hardware resource consumption increases
Solution Approach 1:
The patent segments the program counter values into different categories based on instruction types (jump, branch, return, sequential). Each segment is handled with appropriate compression or recording strategy, avoiding the need for complex universal dictionary coding while achieving effective compression for control flow instructions.
Solution Approach 2:
The patent uses a simplified copying mechanism where recent PC values are stored in a small buffer and reused for sequential instructions. Instead of implementing full dictionary coding, it copies and reuses known PC patterns, achieving compression with minimal hardware resources.
3Loss of information
If all instruction types are recorded in detail, then information completeness is improved, but data transmission bandwidth is consumed
Solution Approach 1:
The patent extracts only the essential path information from all instruction types. By identifying and recording only control flow instructions (jump, branch, return) that actually change program execution paths, it maintains complete path information while eliminating redundant data from sequential instructions that don't affect control flow.
Solution Approach 2:
The patent changes the recording parameters based on instruction type. For control flow instructions, it records full PC values with direction flags. For sequential instructions, it uses inference or omission. This parameter differentiation maintains information completeness for path analysis while reducing overall data bandwidth requirements.
Data Source
AI summary
The present invention provides a program counter compression method and a hardware circuit thereof. The compression method of the present invention includes the following steps: step (1), acquiring execution condition of instructions sent by a processor and classifying and screening said instructions based on said execution condition of the instructions; step (2), executing differential operation on instruction count values of the objective classification and the stall periods based on the classifying and screening result and splicing the obtained differential values; step (3), dictionary encoding the valid differential slicing data segments recorded in step (2). The present invention effectively combines the architecture compression and non-architecture compression and proposes a three-stage compression scheme by organizing and applying classifying and screening, differential encoding and dictionary compression, which drastically increases the compression ratio of the program counter.