Processor Program Counter Interrupt Protection Mechanism
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Solution Overview
Problem
Existing processor systems lack effective methods to detect and ensure the correct handling of interrupt requests, particularly in critical applications where error detection and priority monitoring are crucial.
Innovation Solution
A method and apparatus that protect the program counter structure by comparing the address associated with an interrupt request with a target address, providing a match signal to verify the correct initiation and execution of the interrupt routine, and allowing monitoring of interrupt requests and priority observance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interrupt requests are allowed to be processed in processor systems, then task priority and time-critical task execution are improved, but error detection capability and reliability are worsened due to lack of monitoring mechanisms
Solution Approach 1:
The patent implements a feedback mechanism where the monitor unit continuously observes program counter values during interrupt handling and compares them against expected values. This feedback loop enables detection of errors in interrupt vector retrieval and interrupt service routine execution, thereby improving reliability without compromising interrupt handling efficiency
Solution Approach 2:
The patent introduces a monitor unit as an intermediary component between the program counter structure and the interrupt control device. This monitor unit acts as a mediator that observes and verifies program counter operations during interrupt handling, providing error detection capability without directly interfering with the interrupt processing flow
2Reliability
If monitoring mechanisms are added to detect interrupt handling errors, then reliability and error detection are improved, but device complexity and structural modifications are worsened
Solution Approach 1:
The monitor unit utilizes existing program counter structure outputs and compares them against pre-stored expected values. The system monitors itself by leveraging its own operational data (program counter values) without requiring external monitoring infrastructure, thereby improving reliability with minimal additional complexity
Solution Approach 2:
The patent creates a copy of the expected program counter values in the form of target values stored in memory. The monitor unit compares actual program counter outputs against these copied expected values, enabling error detection without requiring complex real-time calculation or additional hardware structures
3Measurement precision
If address comparison is performed for every interrupt request, then error detection precision is improved, but processing time and productivity are worsened
Solution Approach 1:
The patent performs preliminary actions by pre-calculating and storing expected program counter values (target values) in memory before interrupt handling occurs. During interrupt processing, the monitor unit simply retrieves and compares against these pre-prepared values, maintaining high detection precision while minimizing processing time overhead
Data Source
AI summary
A processor system comprises at least a program counter structure, an interrupt control device, a memory, and an apparatus. The interrupt control device is configured to respond to an interrupt request by providing the program counter structure with an address associated with the interrupt request. The program counter structure is configured to output the address to the memory via a memory interface. The apparatus is configured to protect the program counter structure in case of an interrupt request, the apparatus includes an interface, a comparing device, and an outputting device.