Program Driver Circuit Voltage Limiter for Memory Reliability
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Solution Overview
Problem
Non-volatile memory devices, particularly phase-change memory (PCM) devices, face issues with 'open bits' during writing cycles, leading to damage of memory cells and increased risk of transistor damage due to overvoltage stress.
Innovation Solution
The introduction of a program driver circuit with a limiter circuit, which includes a limiting transistor and a threshold generator circuit, helps to mitigate overvoltage stress by controlling the voltage on the main bitline and local bitline, thereby protecting the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a current pulse of large amplitude is applied to cause the chalcogenic material to return into the high-resistivity amorphous RESET state, then the memory cell can be successfully programmed, but overvoltage stress damages transistors
Solution Approach 1:
A voltage limiter circuit is introduced as an intermediary component between the current pulse generation circuit and the memory cell. This limiter circuit includes a limiting transistor and a threshold generator circuit that work together to cap the maximum voltage at the bitline during programming operations. The threshold generator circuit establishes a safe voltage threshold, and when the bitline voltage approaches this threshold during high-amplitude current pulse application, the limiting transistor activates to clamp the voltage, preventing excessive overvoltage stress on the transistors while still allowing sufficient current to program the memory cell reliably
2Productivity
If high current density is applied to the chalcogenic material to achieve phase change, then programming is effective, but open bits occur leading to transistor damage
Solution Approach 1:
The voltage limiter circuit implements a feedback mechanism where the threshold generator circuit continuously monitors the voltage at the bitline during programming operations. When the voltage reaches the predetermined threshold indicating approaching open bit conditions, the limiting transistor activates to reduce the voltage. This feedback loop allows the system to maintain high current density for effective programming while automatically preventing the voltage conditions that cause open bits and transistor damage
Data Source
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AI summary
A non-volatile memory device including: an array (2) of memory cells (3) arranged in rows and columns; a plurality of local bitlines (BL), the memory cells (3) of each column being coupled to a corresponding local bitline (BL); a plurality of main bitlines (MBL), each main bitline (MBL) being coupleable to a corresponding subset of local bitlines (BL); a plurality of program driver circuits (19' ; 19" ; 19'''), each of which has a corresponding output node (Nout) and injects a programming current (I*) in the corresponding output node (Nout), each output node (Nout) being coupleable to a corresponding subset of main bitlines (MBL;MBL<0>-MBL<3>). Each program driver circuit (19' ; 19" ; 19"') further includes a corresponding limiter circuit (35) which is electrically coupled, for each main bitline (MBL;MBL<0>-MRL<3>) of the corresponding subset, to a corresponding sense node (Nout; MBL<0>-MBL<3>) whose voltage depends, during a step of writing, on the voltage on the corresponding bitline (MBL;MBL<0>-MBL<3>). Each limiter circuit (35) turns off the corresponding programming current (T*), in case the voltage (Vout; VMBL) on any of the corresponding sense nodes (Nout; MBL<0>-MBL<3>) overcomes a reference voltage (Vclamp+Vth40;Vclamp+Vth40').