Program Memory Checking via Independent Counter Traversal
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Solution Overview
Problem
The complexity and safety requirements of automotive ASICs necessitate efficient verification of program codes stored in program memories, particularly for conditionally executable jump instructions that introduce non-determinism in the instruction stream, making existing data block or stream-based verification mechanisms inadequate.
Innovation Solution
An arrangement with an instruction counter that independently traverses the program memory's address space, connected to a register and changeover switches, allows for comprehensive error detection and monitoring of all instruction addresses, including those only accessed in specific modes, using a combination of existing hardware elements and a time-division multiplex method.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data block or stream-based verification mechanisms are used, then verification efficiency is improved, but completeness of program memory checking deteriorates due to non-deterministic instruction streams from conditional jump instructions
Solution Approach 1:
The verification process is segmented into two distinct modes: normal program execution mode and verification mode. The instruction counter is divided into functional segments including a normal instruction counter, a verification counter, and a mode selection mechanism. This segmentation allows the system to separate the non-deterministic normal execution path from the deterministic verification path, enabling complete program memory checking while maintaining verification efficiency.
Solution Approach 2:
The system dynamically switches between normal execution mode and verification mode through a mode selection mechanism. The instruction counter dynamically adapts its behavior based on the current mode: during normal operation it follows the program code's control flow, during verification it sequentially traverses the entire address space. This dynamic behavior resolves the contradiction by providing both efficient normal execution and complete verification coverage.
2Reliability
If an additional verification counter is added to the instruction counter, then completeness of program memory checking is improved, but hardware expenditure and chip area increase
Solution Approach 1:
The verification counter is designed to share hardware resources with the normal instruction counter, including the register and changeover switches. The same register serves both normal instruction addressing and verification addressing purposes. The changeover switches enable the same hardware path to be used for both normal program execution and verification mode. This multi-functionality reduces hardware expenditure while achieving complete program memory checking.
Solution Approach 2:
The normal instruction counter and verification counter are merged into a single counter structure that can operate in two modes. The counter unit, register, and control logic are combined and controlled by a mode selection signal. This merging eliminates redundant hardware while maintaining the ability to perform both normal execution and complete verification of the program memory address space.
3Reliability
If the entire program memory address space is traversed during verification, then completeness of checking is improved, but interruption of normal program flow increases
Solution Approach 1:
The verification process is implemented as a periodic action that occurs at predetermined intervals during normal operation. The system alternates between normal execution periods and verification periods. During verification periods, the verification counter traverses the program memory address space; during normal periods, the instruction counter executes the program code. This periodic approach balances complete checking with minimal disruption to normal program flow.
Solution Approach 2:
The system performs preliminary actions to minimize disruption: before entering verification mode, the current instruction counter value is saved; after verification, the saved value is restored to resume normal execution. This preliminary saving and restoring of the instruction counter state ensures that normal program flow can be seamlessly continued after verification, reducing the perceived interruption time.
Data Source
Figure 1~2
Figure 3
AI summary
The invention relates to an arrangement for checking a program memory (9) in a computation unit having a checking module (11), wherein the computation unit comprises a command counter (8) which is connected to the checking module (11) and which has a register (1), and the register (1) is connected to a first changeover switch (3) which sets the register content. In an arrangement which allows the command addresses of the complete program memory to be checked, the command counter (8) contains a supplementary counter (2, 6, 7) which is connected to the register (1) and which passes through the command address space of the program memory (9) independently of the program code during normal operation.