Program Verification Circuit for Flash Memory
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Solution Overview
Problem
As integration density increases in flash memory devices, the sensing margins decrease, leading to errors and slower programming times in multi-level cell (MLC) flash memory devices, which affects the accurate storage of multi-bit data.
Innovation Solution
A program verification circuit is introduced that includes a failed state counting unit and a failed bit counting unit to selectively count failed bits based on error-correctable bits, generating signals to determine when to activate or deactivate programming loops, thereby optimizing the programming process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integration density is increased in flash memory devices, then storage capacity is improved, but sensing margins decrease leading to errors and slower programming times
Solution Approach 1:
The patent segments the verification process into multiple stages: initial verification, intermediate verification, and final verification. Each stage uses different verification voltages and counting methods tailored to the specific programming state, allowing accurate verification even with reduced sensing margins while maintaining high integration density
Solution Approach 2:
The patent dynamically changes verification parameters including verification voltages (Vref1, Vref2, Vref3), counting thresholds, and verification methods based on the current programming state and threshold voltage distribution. This adaptive parameter adjustment maintains reliable sensing margins despite increased integration density
2Quantity of substance
If integration density is increased in flash memory devices, then storage capacity is improved, but programming time increases
Solution Approach 1:
The verification process is divided into segmented stages with different counting requirements. The failed state counting unit performs coarse verification first, and only activates the failed bit counting unit when necessary, significantly reducing the average verification time while maintaining accuracy for high-density storage
Solution Approach 2:
The patent implements selective counting where the failed bit counting unit is activated only when the failed state count indicates potential failures. This partial action approach avoids unnecessary full counting operations, reducing programming time while ensuring reliable verification for high-capacity devices
3Quantity of substance
If multi-level cell (MLC) flash memory is used to store multiple bits per cell, then storage density is improved, but accurate storage becomes more difficult due to decreased sensing margins
Solution Approach 1:
The patent segments the threshold voltage range into distinct regions (first region for logic 0, second region for logic 1) with intermediate regions for transition states. The verification process separately checks each region using dedicated verification voltages, ensuring accurate multi-bit storage even with reduced sensing margins in MLC devices
Solution Approach 2:
The patent applies different verification strategies to different threshold voltage regions. The failed state counting unit and failed bit counting unit use region-specific verification voltages and thresholds tailored to the local characteristics of each threshold voltage distribution, improving storage accuracy for MLC devices
Data Source
AI summary
A program verification circuit comprises a failed state counting unit and a failed bit counting unit. The failed state counting unit counts failed program states among a plurality of program states, and generates a first program mode signal indicating whether counting of failed bits is required. The failed bit counting unit selectively counts failed bits in response to the first program mode signal, and generates a second program mode signal indicating whether a program operation is completed.