Programmable ADC for Low-Power DC-DC SMPS
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing digital controllers for low-power SMPS in portable devices are sub-optimal due to high power consumption and silicon area requirements, and prior solutions using windowed-based ADC architectures are not feasible in modern IC technologies, limiting the utilization of digital control advantages.
Innovation Solution
A programmable ADC architecture incorporating a sigma-delta DAC and windowed ADC with adjustable delay lines, utilizing a moving average filter effect to reduce silicon area and power consumption, allowing for on-chip implementation and programmable voltage regulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If windowed-based ADC architectures are used, then power consumption is reduced, but manufacturing feasibility in modern IC technologies is lost
Solution Approach 1:
The patent replaces the mechanical/analog windowed-based ADC architecture with a fully digital sigma-delta ADC implementation. This substitution enables the system to maintain low power consumption characteristics while achieving manufacturability in modern CMOS IC technologies through standard digital fabrication processes.
Solution Approach 2:
The patent changes the fundamental operating parameters of the ADC by transitioning from a windowed-based architecture to a sigma-delta architecture with oversampling and digital filtering. This parameter change allows the system to achieve both low power consumption and compatibility with modern IC manufacturing processes.
2Ease of manufacture
If fully digital sigma-delta ADC is implemented, then manufacturing feasibility is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic oversampling at a high frequency followed by digital decimation filtering. This periodic action allows the use of simpler, lower-power digital circuits that operate at lower frequencies while maintaining the benefits of sigma-delta conversion, thereby reducing overall power consumption.
Solution Approach 2:
The patent implements dynamic element matching and programmable oversampling ratios that allow the ADC to adapt its operation based on application requirements. This dynamic operation enables the system to optimize power consumption by adjusting the oversampling ratio and activating only necessary circuit components.
3Measurement precision
If analog controller ICs are used, then voltage regulation accuracy is improved, but system size increases
Solution Approach 1:
The patent merges the ADC, digital filter, and control logic into a single integrated digital controller block that can be implemented in the same CMOS process as the power switch. This consolidation eliminates the need for separate analog controller ICs, reducing system size while maintaining voltage regulation accuracy through precise digital control.
Solution Approach 2:
The patent creates a universal digital controller architecture that can regulate multiple output voltages and adapt to different power management requirements. This multi-functional digital controller replaces multiple application-specific analog controller ICs, reducing overall system size while maintaining or improving regulation accuracy through programmable parameters.
Data Source
AI summary
A voltage-to-time based windowed analog-to-digital converter (ADC) can have programmable reference voltage, conversion time, and accuracy of voltage regulation. The ADC can be fully implemented on a small silicon area and is suitable for implementation in various integrated digital controllers for high-frequency low-power switch-mode power supplies (SMPS). The programmable characteristics can be achieved through the utilization of the inherent averaging effect of the delay line or of the other voltage-to-time conversion structures and through the adjustments of delay cells' propagation times or the effective voltage-to-time conversion ratio in alternative structures.