Programmable Address Stride Memory for Parallel Access
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Solution Overview
Problem
In multiple processor systems, existing memory technologies are unable to efficiently access and precharge memory cells at different address strides, leading to a decline in desirable attributes such as cost-effectiveness, operating power, bandwidth, and latency.
Innovation Solution
A digital memory device configured to receive, store, and output address strides of different sizes, allowing multiple processors to access and precharge memory cells independently with varying address strides, using programmable look-up tables to dynamically adjust stride lengths based on past accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single address stride is used for all processors, then device complexity is reduced, but productivity and system performance deteriorate due to inability to optimize for different applications
Solution Approach 1:
The memory access control functionality is segmented into separate address stride generation units for each processor. Each processor has its own programmable address stride logic that can be independently configured, allowing different address strides for different applications without requiring a completely separate memory controller for each processor.
Solution Approach 2:
The address stride is made dynamic and programmable rather than fixed. The memory device includes programmable look-up tables that can be dynamically configured to provide different address strides based on the specific application requirements, enabling optimization for various workloads while using the same physical memory hardware.
2Productivity
If multiple processors access memory simultaneously with different address strides, then productivity improves, but device complexity increases due to need for independent address stride control
Solution Approach 1:
The address stride control is segmented into independent units for each processor, with each processor having its own programmable address stride generation logic. This segmentation allows simultaneous independent operation of multiple processors with different address strides without requiring a complex centralized controller.
Solution Approach 2:
The memory device is designed with universal programmable address stride logic that can serve multiple processors simultaneously. The same memory hardware supports multiple address stride patterns through programmable look-up tables, eliminating the need for separate dedicated memory access paths for each processor.
3Ease of operation
If fixed address stride is used, then ease of operation is maintained, but adaptability deteriorates when applications require varying address strides
Solution Approach 1:
The address stride is transformed from a fixed parameter to a dynamic, programmable value. Programmable look-up tables are incorporated into the memory device, allowing the address stride to be dynamically adjusted based on application requirements while maintaining a simple interface for configuration through software or control signals.
Solution Approach 2:
The address stride parameter is made changeable and adaptable. The memory device includes programmable logic that can modify the address stride parameter in response to different application needs, enabling optimization for various workloads such as sequential access, random access, or cache-line aligned access patterns.
Data Source
AI summary
Embodiments of the present disclosure provide methods, apparatuses and systems including a storage configured to store and output multiple address strides of varying sizes to enable access and precharge circuitry to access and precharge a first and a second group of memory cells based at least in part on the multiple address strides during operation of the host apparatus/system, the first and second group of memory cells being different groups of memory cells.