Programmable Processing Array for Wireless DFE Throughput
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional programmable processing arrays face inefficiencies in implementing digital front-end (DFE) processing operations, particularly in signal processing for wireless systems, due to limitations in handling unaligned data access and the need for high throughput at low power levels, which is challenging for current vector/VLIW DSP architectures.
Innovation Solution
The implementation of a programmable processing array architecture with local buffers and unicast/multicast butterfly networks, along with multiplication and adder units, enables efficient DFE processing operations by accommodating various filter types and reducing computational energy requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional vector/VLIW DSP architectures are used for DFE processing, then basic processing functionality is provided, but processing throughput is insufficient and power consumption is high
Solution Approach 1:
The processing array is divided into multiple independently controllable processing elements (PEs) that can be selectively activated. Each PE contains dedicated buffers and computation units, allowing the system to segment the processing workload and activate only the necessary number of PEs for each filtering operation, thereby improving throughput while reducing power consumption by keeping inactive PEs in low-power states
Solution Approach 2:
The architecture implements dynamic reconfiguration capabilities where the processing array can be dynamically programmed to support different filter types (FIR, IIR, half-band, fractional-band) and operating modes. The control logic dynamically adjusts the activation and configuration of processing elements based on the specific processing requirements, enabling high throughput for demanding operations while conserving power during simpler tasks
2Adaptability or versatility
If conventional programmable processing arrays are used, then general processing capability is provided, but handling of unaligned data access is inefficient
Solution Approach 1:
The architecture introduces specialized buffer structures and data alignment logic as intermediary components between the memory system and processing elements. These buffers include dedicated logic for handling unaligned data access patterns, automatically performing data reorganization and alignment operations without requiring complex control logic in the main processing path, thereby maintaining high processing efficiency while providing flexible data access patterns
Solution Approach 2:
Each processing element is equipped with local buffers and data alignment logic specifically optimized for handling unaligned access patterns. This local capability allows each PE to independently and efficiently process unaligned data without requiring global coordination or complex memory access control, maintaining high processing efficiency while providing adaptability for various data access patterns
3Adaptability or versatility
If multiple filter types are supported on separate platforms, then comprehensive filtering capability is achieved, but device complexity increases
Solution Approach 1:
The processing array implements a universal architecture where a single set of processing elements can be dynamically reconfigured to support multiple filter types including FIR, IIR, half-band, and fractional-band filters. The same physical hardware resources (processing elements, buffers, interconnect) are reused across different filter implementations through dynamic programming, eliminating the need for separate dedicated platforms for each filter type while maintaining comprehensive filtering capability
Solution Approach 2:
The architecture supports different filter types by dynamically changing operational parameters such as coefficient memory organization, data flow patterns, and processing element configuration rather than requiring structural changes. The same hardware platform can be reprogrammed to implement different filter algorithms by loading appropriate coefficient sets and configuring the control logic, thereby achieving versatile filter support without increasing physical device complexity
Data Source
AI summary
Techniques are disclosed for the implementation of a programmable processing array architecture that realizes vectorized processing operations for a variety of applications. Such vectorized processing operations may include digital front end (DFE) processing operations, which include finite impulse response (FIR) filter processing operations. The programmable processing array architecture provides a front-end interconnection network that generates specific data sliding time window patterns in accordance with the particular DFE processing operation to be executed. The architecture enables the processed data generated in accordance with these sliding time window patterns to be fed to a set of multipliers and adders to generate output data. The architecture supports a wide range of processing operations to be performed via a single programmable processing array platform by leveraging the programmable nature of the array and the use of instruction sets.