Programmable Attenuator Circuit for Parallel Analog Timing Tests
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Solution Overview
Problem
Existing automatic test equipment (ATE) testers are limited in their ability to concurrently test multiple devices due to a restricted number of time stampers (TSs), particularly for high-speed digital TSs, and cannot accommodate DUTs operating at high voltages, leading to inefficiencies in parallel test efficiency (PTE) and increased production costs.
Innovation Solution
The implementation of a programmable gain attenuator circuit with multiple stages, including resistors, amplifiers, and a gain control circuit, allows for adjustable signal attenuation, enabling the use of a larger number of low-power universal TSs to test high-voltage DUTs, thereby enhancing PTE and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a limited number of high-speed digital time stampers are used to test high-voltage DUTs, then measurement precision is maintained, but parallel test efficiency deteriorates due to the small number of concurrent tests possible
Solution Approach 1:
The patent introduces an intermediary circuit (attenuator with amplifier) between the high-voltage DUT and the low-voltage time stamper. This intermediary adapts the high-voltage signal to a level suitable for the time stamper, enabling the use of multiple low-power time stampers instead of being limited to a few high-voltage capable units, thereby improving parallel test efficiency while maintaining measurement precision
Solution Approach 2:
The patent changes the voltage parameter of the signal through programmable attenuation. By dynamically adjusting the attenuation level, the system can accommodate different DUT voltage levels using the same low-voltage time stampers, enabling higher parallel test efficiency without sacrificing measurement accuracy
2Device complexity
If low-power general purpose analog time stampers are used to test high-voltage DUTs, then device complexity is reduced and cost is lowered, but the ability to accommodate high-voltage DUTs deteriorates
Solution Approach 1:
The attenuator circuit serves as an intermediary that bridges the voltage gap between low-power time stampers and high-voltage DUTs. This allows simple, low-cost time stampers to test high-voltage devices by adapting the voltage level, thereby maintaining low device complexity while achieving high adaptability to different DUT voltage requirements
Solution Approach 2:
The patent makes low-power general purpose analog time stampers universal by adding the attenuator circuit. This single time stamper design can now handle multiple DUT types with different voltage levels (e.g., 5V, 12V, 24V, 48V) through programmable attenuation, eliminating the need for different time stamper models for different voltage requirements
3Productivity
If multiple high-voltage capable time stampers are deployed to increase parallel test efficiency, then productivity is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
Instead of deploying multiple expensive high-voltage time stampers, the patent uses an intermediary attenuator circuit that enables multiple inexpensive low-voltage time stampers to handle high-voltage signals. This approach achieves the same parallel test efficiency while significantly reducing device complexity and manufacturing cost
Solution Approach 2:
The patent replaces expensive, complex high-voltage time stampers with cheaper, simpler low-voltage time stampers combined with attenuator circuits. This substitution reduces both device complexity and manufacturing cost while maintaining or improving parallel test efficiency through the use of multiple inexpensive units
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The attenuator circuit facilitates high-volume, parallel testing of electronic devices with improved accuracy and precision, allowing up to 96 concurrent tests on a Teradyne ETS-800 ATE tester, reducing production costs and optimizing test efficiency by accommodating a variety of device designs without hardware changes.
Implementation Method 1
The second circuit has a second input, a second output, and a first amplifier circuit, the second input coupled to the first output, and the first amplifier circuit coupled between the second input and the second output
Implementation Method 2
The third circuit has a third input, a third output, a second amplifier circuit, and a gain control circuit, where the third input is coupled to the second output, the second amplifier circuit is coupled between the third input and the third output
Implementation Method 3
the gain control circuit is configured to adjust a gain of the second amplifier circuit
Implementation Method 4
the first circuit has a first input, a first output, a first resistor coupled between the first input and the first output, and a second resistor coupled between the first output and a reference node
Data Source
AI summary
An attenuator circuit for testing electronic devices includes a first circuit having a first input, a first output, a first resistor coupled between the first input and the first output, and a second resistor coupled between the first output and a reference node, a second circuit having a second input, a second output, and a first amplifier circuit, the second input coupled to the first output, and the first amplifier circuit coupled between the second input and the second output, and a third circuit having a third input, a third output, a second amplifier circuit, and a gain control circuit, the third input coupled to the second output, the second amplifier circuit coupled between the third input and the third output, and the gain control circuit configured to adjust a gain of the second amplifier circuit.