Programmable Bank Selection for Shared Memory Subsystems
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Solution Overview
Problem
Existing memory architectures face challenges in enabling efficient and cost-effective access for processor devices to multiple shared memory banks, particularly in terms of programmability, access time, and energy consumption, as current designs struggle to distribute access evenly across banks and assign banks to individual processing elements.
Innovation Solution
A programmable memory system that allows processor devices to access multiple memory banks by generating select signals based on predetermined address bit values, using programmable logic devices and multiplexers to select memory storage structures, and optionally applying hash functions for efficient bank selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If banked memory architecture is used to improve memory access efficiency and energy consumption, then memory access time and energy efficiency are improved, but device complexity increases due to control logic overhead
Solution Approach 1:
The patent combines multiple memory banks into a unified banked memory structure with shared control logic. The system merges the functionality of multiple independent memory units while using a common address bus and control mechanism, thereby improving memory capacity and access efficiency without proportionally increasing control logic complexity.
Solution Approach 2:
The control logic is designed to handle multiple memory banks universally through a single set of control signals. The address decoding logic can selectively activate different banks based on address bits, allowing the same control structure to manage multiple banks efficiently without requiring dedicated control logic for each bank.
2Speed
If memory banks are assigned to individual processors to reduce access congestion, then access time is improved, but device complexity increases due to multiplexed access control
Solution Approach 1:
The memory system is segmented into multiple independent banks that can be accessed simultaneously by different processors. Each bank can handle memory requests independently, allowing parallel access operations that reduce congestion and improve overall memory access speed for multiprocessor systems.
Solution Approach 2:
The patent introduces bank selection as an additional dimension in the memory address space. By using specific address bits to select which bank to access, the system enables multiple processors to access different banks simultaneously, effectively adding a dimensional layer to memory organization that resolves access conflicts without complex multiplexing.
3Area of stationary object
If shared banked memory is used to reduce chip area, then area is reduced, but manufacturing precision requirements increase due to timing bottlenecks
Solution Approach 1:
Multiple memory banks are merged into a single integrated memory structure with unified control logic. This consolidation reduces the overall chip area compared to having completely separate memory units for each processor, while the shared control architecture simplifies timing management across all banks.
Solution Approach 2:
The system uses address bit manipulation and bank selection parameters to dynamically control which memory bank is accessed. By changing the interpretation of address bits based on the selected bank, the system can route memory requests to appropriate banks with optimized timing, reducing timing bottlenecks without increasing chip area.
Data Source
AI summary
A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.