Programmable BIST Architecture Reducing Memory Test Area Overhead
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Solution Overview
Problem
Conventional programmable built-in self-test (BIST) architectures for integrated circuits require large area overhead for storing complex test instructions, limiting their ability to perform multiple complex self-test procedures efficiently, especially when testing complex memory devices like DRAM.
Innovation Solution
A programmable BIST architecture that utilizes a set of registers to store and program large instruction sets element by element, reducing area overhead and enabling flexible, at-speed testing of memory devices with features like programmable repeat functions, retention tests, and dynamic disturb fault testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a separate dependent embedded memory is used to store test instructions, then the BIST circuit can perform complex self-test procedures, but the area overhead increases significantly
Solution Approach 1:
The patent merges the test instruction storage function into the existing memory array structure by utilizing spare rows or columns that are already part of the memory device. This integration eliminates the need for a separate dependent embedded memory, thereby reducing area overhead while maintaining the capability to store and execute complex self-test procedures.
Solution Approach 2:
The patent makes the memory array serve multiple functions: it performs both normal data storage operations and self-test instruction storage. By using the same physical structure for both purposes, the design achieves multi-functionality, reducing the additional area required for test instruction storage while maintaining versatility in testing capabilities.
2Adaptability or versatility
If a large instruction set is used for testing complex memory devices, then multiple complex self-test procedures can be performed, but the area overhead becomes prohibitively large
Solution Approach 1:
The patent segments the test instruction set into smaller, manageable units that can be stored in the spare rows or columns of the memory array. This segmentation allows complex test procedures to be broken down into discrete instructions that fit within the available storage space, enabling multiple complex self-test procedures without requiring prohibitively large area overhead.
Solution Approach 2:
The patent utilizes the vertical dimension of the memory array by incorporating spare rows or columns that extend the storage capacity in a different spatial dimension. This dimensional approach allows additional test instructions to be stored without increasing the footprint area, effectively adding storage capacity along the height or width of the existing array structure.
Data Source
AI summary
A system that provides large instruction sets for testing memory yet reduces area overhead is disclosed. The system for testing a memory of an integrated circuit comprises a set of registers providing element based programmability for a plurality of tests, wherein each test includes a plurality of test elements; a finite state machine for receiving a plurality of test instructions from the set of registers, wherein the finite state machine dispatches signals instructing a test pattern generator to generate a test pattern; a memory control module for applying the generated test pattern to the memory; and a comparator module for comparing a response received from the memory to a stored, known response.